Electronics Forum | Tue May 04 22:54:54 EDT 2004 | davef
Yeh, the IPC courtyards are for old ladies. I want to say that at one time IPC was talking about a new set of rules. Maybe, 7351 - SMT Footprint Design Guidelines??? Anyhow, Jim Blankenhorn at SMTPlus [ sales@smtplus.com ] has done THE best job o
Electronics Forum | Wed Jul 22 20:07:50 EDT 2020 | eptac
You may visit the EPTAC website http://www.eptac.com and select training/classes and then locate IPC Designer Certification. Click on this and you can download a datasheet on the Designer course.
Electronics Forum | Wed Sep 13 03:25:43 EDT 2017 | sbar5781
Any insight appreciated!
Electronics Forum | Tue Jun 13 08:33:11 EDT 2006 | davef
IPC-2222, 5.3.1 defines the parameters of making scoring cuts and the tolerance of the cuts, but does not specify the cuts. Our spec for 0.062" thick FR-4 boards is: 0.018-0.024"
Electronics Forum | Wed Jul 24 17:25:01 EDT 2019 | davef
Your solder stencil design should follow all basic rules for solder stencil design are followed in accordance with IPC-7525 including adherence to an area ratio of 2:3 or greater and an aspect ratio of 1.5 or greater.
Electronics Forum | Thu Oct 26 17:48:47 EDT 2000 | Dave F
In response to your questions: 1) Suggestions on substrate material FR-4 or something better? Most PBGA are on BT. That might good for you, also. 2) Are there design guidelines for wire bonding pattern on the substrate? Several things: 1 Doesn�t
Electronics Forum | Mon Jan 12 21:31:26 EST 2015 | warwolf
The closer your inspection the more defects you will find, the more rework you do the possible cost you will add and the potential increase of damage you could do to your products if rework is not up to a machine copyable standard. "Is there any in
Electronics Forum | Tue Dec 30 09:31:52 EST 2014 | rgduval
I've always approached it like this: Design your processes and perform your work to class three standards, and inspect to the standard that is acceptable. That is, all work should be performed to the highest degree of quality. When the work is ins
Electronics Forum | Thu Jul 18 13:11:56 EDT 2002 | gdstanton
Steve, We are touching up 6 - 12% of all solder joints processed. We consider the solder joint to be the focal point of the SMT process. Therefore our metric is based on it. For example in a given month we... 1. Assembled 25pcs of 'A' (IPC-A-610/J
Electronics Forum | Thu Nov 08 07:33:23 EST 2007 | hussman
Why? Just use IPC on finished solder joints as your guide. I've seen groups of people puts hundreds of hours into this task and then tell me a 3 mil stencil is all I need. After reflow, none of the solder joints meet IPC Class 1 and a lot of tombs
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