Electronics Forum: microvias (Page 2 of 5)

Lo Behold Voids!!!!

Electronics Forum | Thu May 20 11:55:04 EDT 1999 | Parvez

hi everybody, We've been doing some studies on assembly of CSPs. We assembled these packages on micrivia-in-pad patterns. These are 15/13.5/11 mil pads with 6 mil design microvia, using photo/laser/plasma tech. We are seeing voids, as big as the micr

Via-in-pad

Electronics Forum | Fri Mar 04 11:30:46 EST 2005 | Steve

Is anybody using via-in-pad under a BGA successfully? Is this a specialized capability, or do most board houses have the capability to do micro-via's? How small does the via need to be in order to avoid solder wicking? I understand that in order for

Void control

Electronics Forum | Thu Oct 11 13:10:04 EDT 2012 | anvil1021

We are experimenting with void control in reflow and have had pretty good luck for the most part in attaining Class lll IPC spec. but we have seen a sudden increase in voiding on a specific product and I was wondering if anyone has seen this extreme

Void control

Electronics Forum | Mon Oct 15 08:24:24 EDT 2012 | scottp

You could pay the extra to have the microvias plated shut and planarized. If your voids are larger than 25% of the BGA joint area then I would suspect a solderability problem. Either the board plating or a solder paste problem. If they're less tha

Re: Lo Behold Voids!!!!

Electronics Forum | Thu May 20 22:42:19 EDT 1999 | Dave F

| hi everybody, | We've been doing some studies on assembly of CSPs. We assembled these packages on micrivia-in-pad patterns. These are 15/13.5/11 mil pads with 6 mil design microvia, using photo/laser/plasma tech. We are seeing voids, as big as the

via under a smd pad ?

Electronics Forum | Fri Nov 23 16:32:05 EST 2007 | davef

There a several things you can do to prevent the solder wicking down the hole with the current design, and that's where you should focus. Cost goes up as you go down the list, but in neither case do you need to respin the board, have solder starvatio

ALIVH PCB

Electronics Forum | Tue Jul 22 09:05:14 EDT 2003 | davef

Any-Layer Interstitial [Inner] Via Hole (ALIVH). In printed circuit board fabrication, a registered mark of Matsushita Electric for a filled microvia structure in all layers for applications requiring small-size, lightweight build-up PWB to achieve

via under a smd pad ?

Electronics Forum | Wed Nov 14 13:05:40 EST 2007 | rgduval

I had one project with micro-vias in 0805 and larger pads, with no issues. But my most recent project had vias that were larger than the 0402 pads that the via was in. To the point that for a number of the lands, there was no visible pads (a couple

Re: Lo Behold Voids!!!!

Electronics Forum | Fri May 21 14:22:56 EDT 1999 | Dave F

| Dave, | i tried reflowing bare boards with only solder printed on em and no component placed. we still got voids as same as when components were placed. so atleast one of that theories(voids due to component/component placement)could be considered

Assembly of CSP on pads with vias.

Electronics Forum | Sat Jan 23 09:36:35 EST 1999 | Parvez Patel

Hi Everyone, We plan to build, for reliability/experimental/research purpose some CSPs (namely Tessera microBGA 46-I/O 0/75mm pitch and TI 64 I/O 0/8 mm pitch). the various factors that we plan to evaluate are the reliability and assembly concerns fo


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