Electronics Forum | Mon Oct 06 04:03:39 EDT 2003 | iman
Does the EIA standard recommend any standard PCB pad sizes (LxB)? and pitch-to-pitch (Pad) distances? Thanks for the advise.
Electronics Forum | Fri Oct 08 17:03:03 EDT 1999 | Dave F
| Hi, | | Help! Could anyone help to enlighten me on this? | | Question: | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a normal water cl
Electronics Forum | Thu Jan 03 02:35:18 EST 2002 | ianccy
Hi, I am trying to write SOP about the baking requirement of some CSP and uBGA components, the label on the packing said its usable within 72 hours and follow the MSL 4 condition, what does the MSL means? is it Material Safety Level? Has anything to
Electronics Forum | Thu Jan 03 02:36:04 EST 2002 | ianccy
Hi, I am trying to write SOP about the baking requirement of some CSP and uBGA components, the label on the packing said its usable within 72 hours and follow the MSL 4 condition, what does the MSL means? is it Material Safety Level? Has anything to
Electronics Forum | Mon Oct 06 08:51:26 EDT 2003 | davef
The EIA does not provide that information. EIA standards focus on component dimensions. Alternately consider: ...cut... SM-782A - Surface Mount Design & Land Pattern Standard, Inc. Am. 1 & 2 ANSI Approved Get up-to-date land pattern recommendat
Electronics Forum | Fri Oct 03 09:00:18 EDT 2003 | davef
EIA standard packages have a variety of L/W proportions. EIA||Dimension mm (LXW)||Proportion (L/W) 0201||0.6X0.3||2 0202||0.5X0.5||1 0303||0.8X0.8||1 0402||1.0X0.5||2 0504||1.25X1.0||1.25 ||1.4X1.4||1 0603||1.6X0.8||2 0805||2.0X1.25||1.6 1111||2.8X2
Electronics Forum | Wed Oct 06 00:26:04 EDT 1999 | Karlin
| Hi, | | Help! Could anyone help to enlighten me on this? | | Question: | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a normal water cl
Electronics Forum | Wed Oct 06 08:41:42 EDT 1999 | Dave F
| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n
Electronics Forum | Wed Oct 06 12:03:12 EDT 1999 | Graham Naisbitt
| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n
Electronics Forum | Wed Oct 06 23:36:28 EDT 1999 | karlin
| | | Hi, | | | | | | Help! Could anyone help to enlighten me on this? | | | | | | Question: | | | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z
