Electronics Forum | Thu Jun 30 03:14:34 EDT 2016 | andrzej
Looks like "black pad" issue. More about this here: http://www.ipc.org/feature-article.aspx?aid=Black-pad Definitly PCB supplier need to improve the process.
Electronics Forum | Thu Sep 06 05:25:38 EDT 2018 | spoiltforchoice
I'm no expert but I think you will find the majority of discussions around BGA & good printing results focus on the PCB design and things like tented vias and pad definition. e.g https://macrofab.com/blog/bga-pad-creation-smd-nsmd/ After that, work
Electronics Forum | Mon Oct 21 19:17:23 EDT 2013 | hegemon
The first picture shows an issue. Note that the vias adjacent to the interior rows are filled with solder. At the outside rows this is not evident. What you might have are interior spheres that are smaller in volume than the rows on the outide, si
Electronics Forum | Wed Jul 09 16:01:10 EDT 2003 | russ
Mike, the one pad that is "small" definitely appears to be over etching (It looks like it was supposed to be much larger). What is the dims of this little bugger as compared to the Gerber? i would also tend to believe that there probably is some mask
Electronics Forum | Thu May 10 02:58:00 EDT 2018 | robl
Hi Dex, We're going back a few decades here, but... 1) can you treat it as 4 large leads - one rectangular block per side? 2) Is it failing on the coplanarity check set up or the basic vision? if Coplanarity, can you skip that check? 3) are you us
Electronics Forum | Thu Jan 29 00:10:17 EST 2004 | Vinny
Hi Dave, Thanks for your reply. I have tried getting the design changed from the customer but they cannot provide thermal relief as this changes the RF performance and they cannot afford to do that. As for profile it does reach the reflow tempera
Electronics Forum | Wed Jun 11 12:03:29 EDT 2003 | rmurtuza
I have the speed data set at 0.12S for the small caps and in addition to that I am using an overall tact time reduction of 14 to 16 seconds. If I use the default overall tact time then I have placement defects such as components being placed: 1. Twi
Electronics Forum | Tue Mar 04 11:28:46 EST 2008 | clampron
Good Morning, I have an application that we are tooling up for that has several LGA (Land Grid Array) components. The Gerber files from the customer has a solder paste definition of 1:1 to the pad. As I look at this part, I cannot believe that this
Electronics Forum | Mon Sep 20 13:04:25 EDT 2004 | davef
The Intel BGA Developer�s Guide [ http://developer.intel.com/design/packtech/ch_14.pdf ] says: 14.8.3.3 Plated Through Hole (PTH) Isolation Regardless of the technique used for the mounting pads shape or definition, isolation of the plated through h
Electronics Forum | Fri Jun 30 10:42:24 EDT 2000 | Chrys Shea
That pad had a 16 mil dia, so I arrived at 20 mil squares by adding 2 mils to each side of the pad. Following that logic, a 12 mil pad would use a 16 mil square. But a 12 mil pad is on a finer pitch that isn't mentioned, so you should definitely
