Electronics Forum | Sat Oct 19 11:48:39 EDT 2002 | davef
Good points, John. Continuing to track on the voiding issue, why remove voids anyhow? * Voids are primarily process indicators. There is experimental evidence that voids retard crack propagation locally around the void on at least on a temporary bas
Electronics Forum | Mon Sep 30 20:41:25 EDT 2002 | jason
Hi, The acceptance level for voids is 25% and most of it on your case should be the paste. If you want to reduce / eliminate it, you gotta have the Production to practise FIFO for the usage of the paste. If it is expired paste or exposed to long
Electronics Forum | Sat Oct 19 08:33:50 EDT 2002 | johnw
The whole thread seem's to have gone off track. Russ we've been doing a fairly big bit of work on the whole BGA voidign thing as we were so unhappy with the answer's that we were getting from around the industry, basically no one really kows all the
Electronics Forum | Thu Mar 25 11:30:33 EDT 2010 | Sean
Hello Rajeshwara, If not mistaken, the 25% solder void specification is for BGA...As I I as know, no specification given to mosfet component yet..I think you are right, I need to look at the stencil aperture in order to reduce the air trap underneat
Electronics Forum | Wed Mar 24 10:28:51 EDT 2010 | Sean
Hi all, Anyone used to come across solder void underneath mosfet as shown in the attached file? Will this pose any reliability issue, such as get burnt during functional test? How to over come this problem? As far as I know there is no acceptabl
Electronics Forum | Wed Mar 24 11:09:44 EDT 2010 | rajeshwara
Hello Sir I faced the same problem for QFP in DTH product in India. IPC stated that void should not be more than 25% of solder joint. But this type of void definatly create problem during functional test. Please check the folloeing point... 1.Check t
Electronics Forum | Thu Mar 25 12:34:26 EDT 2010 | bgaguy
the voids will cause a long term relability problem as the part will not be correctly heatsinked. Change your stencil aperature to a "+" sign 15-20 mils wide in the center of the pad. ___________ : | : : | : :----|----: : | : :__
Electronics Forum | Fri Mar 26 09:34:01 EDT 2010 | dyoungquist
What about thermal cycling and/or vibration over the long term? My guess is that with the voids the joint would not be as reliable long term as a joint without the void. Am I thinking correctly?
Electronics Forum | Fri Mar 26 03:24:01 EDT 2010 | ravikumarasahitec
Hi, yes we used to see this kind of problem our customer end. This due to stencil aperture opening.these kind of issues we will overcome thorough our stencil process. please contact. ravikumar@asahitec.in
Electronics Forum | Fri Mar 26 00:57:05 EDT 2010 | 89jeong
Hello Sir. We also have faced a same problem. At that time, we had to repair it because we could not find any solution. But in our experience, the void underneath FET was more severe whenever we used the FET that have been made long time ago. It is
