Electronics Forum | Fri Oct 28 14:09:39 EDT 2022 | ttheis
Allowing a part to go over the board boundaries can cause collisions when boards are nested. The software on these machines has limitations but it is plenty capable and rooted in preventing physical damage to the machine. Once you are familiar with t
Electronics Forum | Thu Jul 08 12:33:52 EDT 1999 | Mike Demos
Thank you all for your replies. Thanks to your replies and backup from the IPC-SM-782A (section 3.6.3.2) and James Blankenhorn's "SMT Design Rules & Standards," the designer has agreed to provide adequate clearance between the via and the pad. I wi
Electronics Forum | Mon Aug 20 15:53:52 EDT 2007 | erhard
Manufacturing already tried to get a design change but no chance. I guess because the designer is afraid the components could get bent too much if they are mounted with a stand off. Of course everyone who has to manufacture this fist sais: why don't
Electronics Forum | Thu Jul 13 22:20:38 EDT 2000 | Dave F
=10 mils larger than lead 3 silk screen legend text weight >=10 mils 4 pads >=15 mils larger than finished hole sizes 5 place through hole components on 50 mil grid 6 no silk screen legend text over vias (if vias not solder masked) or holes 7 so
Electronics Forum | Tue Sep 14 18:27:37 EDT 2004 | MikeF
I would need a little more information to be able to rule out some of the possible causes. Have you checked to see if the pins with the minimal solder have anything in common, do all have traces to them? or internal power or ground plane connections?
Electronics Forum | Sat Dec 02 21:21:11 EST 2000 | Murad Kurwa
Our NPI division is in a same category. We assemble small quantities and lot of different set-ups. I created a DPMO charting method using Excel that we use at Post Reflow, Post Wave and Final QC. In addition, we use x-r charts at screen print for con
Electronics Forum | Tue May 29 20:22:19 EDT 2001 | davef
Well, no fault with your calculations from here. They appear to be correct. [Logic doesn't appear to be off to far off base, either. An epiphany, eh?] As mentioned in an earlier posting on this thread, consider following the recommendations of IP
Electronics Forum | Wed Aug 13 21:03:01 EDT 2003 | davef
Your dust collection / humidity / ionic path concern is reasonable. Consider applying your conformal material thick enough to form a good barrier between the device edge and the board, similar to what you do for QFP. [Admittedly the QFP is not a pre
Electronics Forum | Mon May 20 16:15:48 EDT 2019 | davef
Resources are: * IPC-7525A - Stencil Design Guidelines, 3.5.2 Step-Up Stencil This type stencil is useful when it is desirable to print thicker solder paste in a small portion of the stencil. An example would be a ceramic BGA where it is necessary t
Electronics Forum | Thu Jul 08 15:38:27 EDT 1999 | Earl Moon
| Thank you all for your replies. Thanks to your replies and backup from the IPC-SM-782A (section 3.6.3.2) and James Blankenhorn's "SMT Design Rules & Standards," the designer has agreed to provide adequate clearance between the via and the pad. |
