Electronics Forum | Thu May 09 08:36:18 EDT 2019 | solderkingchris
Hi, You can work on improving stencil design, having the perfect profile and other process improvements but it may be the paste itself letting you down. We have put a lot of work into developing our solder pastes to significantly reduce voiding. Y
Electronics Forum | Tue Jul 30 07:29:06 EDT 2013 | scotceltic
We are currently experiencing thermal shock failure on a BGA package. We are currently looking at improvements to improve the thermal shock properties by using underfilm. I have seen some studies out there that use this process to improve drop test
Electronics Forum | Wed Aug 20 20:10:30 EDT 2008 | davef
Naw, accounting is boring. Standoff could be an issue. Coupla things: * Above 30 thou, just about any cleaning process, more sophisticated than a garden hose, will produce acceptable results * Below 10 thou, can be cleaned with best efforts, but not
Electronics Forum | Fri Feb 20 16:39:51 EST 1998 | Jim Blankenhorn
| I have developed a method to increase SMT circuit density | up to 40%. Looking for interested PCB fabricators and | designers for process improvement. Tell us more. How can it be done and what does it take from a design level. What about solder dra
Electronics Forum | Fri Feb 20 16:34:41 EST 1998 | Jim Humecky Amdahl Corp
| I have developed a method to increase SMT circuit density | up to 40%. Looking for interested PCB fabricators and | designers for process improvement. Earl, What are you doing now. What you're suggesting can't be done without trickery. We've been d
Electronics Forum | Mon Aug 02 11:16:38 EDT 2010 | sdibuyer
Can anyone recommend a reputable / knowledgeable SMT expert in the Bay Area to work on a contract / consultant basis? 10-20 hours per week for 3 - 6 months. This person will assess solder joint health, drive DOEs to maximize results within existing c
Electronics Forum | Mon May 06 06:22:39 EDT 2019 | SMTA-Rogers
Hello! Do you have a better stencil design to reduce the large area of solder joint voids? Or is there a suggested way to set the reflow profile? Or are there other process improvements to make the solder joint at the LED pad less than 10% per void?
Electronics Forum | Thu Nov 16 18:19:10 EST 2000 | Dave F
We want to improve our process for accepting SMT solder paste stencils received from suppliers. Our process: * E-mail CAD aperatures to supplier with "readme" giving specific fabrication instructions to the supplier. * Receive stencil from the suppl
Electronics Forum | Tue Dec 07 22:25:45 EST 1999 | sin
Dave, the zero-defect is impossible through my understand in a high volume or proto run manufacturing. Base on theory i have read, yes of course it should be. but practical side of view, it is impossible. you are talking about plenty of variable to
Electronics Forum | Tue Dec 07 10:59:46 EST 2004 | mevishu
Dear all. I am working on project to improve the productivity of palcement machine of my company .My prime cocern is CPH i.e components placed per hour. Rated capacity is 48000 componets/hour and what we actually acgieve is 23000. No doubt this mu
