Electronics Forum | Wed Jan 01 22:19:33 EST 2020 | sssamw
Solder ball attached on solder joint without violation minimum electrical clearance is acceptable. If your process parameter including stencil not changed, suggest you check if solder pasted being pushed out after IC placement, also check if solder j
Electronics Forum | Fri Jan 03 11:37:24 EST 2020 | emeto
Sometimes might be internal change with personnel. Issue is actually there, but if no one questions it-it is not an issue. With 7mil stencil there is a good chance to have solder balls. So were they registered or were they fixed/cleaned?
Electronics Forum | Thu Jan 02 10:30:42 EST 2020 | emeto
thank you Steve, when you mention Stencil design, what do you refer to? How about the Reflow profile? Any specifics that I should look for. Everything is in my process window, but some detail towards this package might be very helpful.
Electronics Forum | Fri Jan 03 02:03:58 EST 2020 | sssamw
What's your target for voiding? I cannot see it violate 25% of solder joint area. Process setting and PCB design can impact the voiding, many factors, such as PCB pad, stencil aperture and thickness, re-flow profile, solder paste, etc.
Electronics Forum | Fri Jan 03 12:48:23 EST 2020 | cyber_wolf
Besides correct stencil design, solder paste chemistry can have a profound effect on voiding. People will tell you reflow profiles. I have never in my career seen a reflow profile have any effect on voiding unless it is grossly off.