Electronics Forum | Tue May 05 08:57:14 EDT 1998 | Cunli Jia @ SMTnet
Everyone, The PCB Capital Equipment Mart has been open to the public since Monday, May 4. This new service was designed for you, the equipment vendors and users, with input from some of you. All of you can post free ads of quipment for sale or wa
Electronics Forum | Fri May 29 11:10:40 EDT 1998 | Chris Ellis
John, I sell preowned and reconditioned PCB assembly equipment for a company called Insertech. We would have several pieces that would meet your needs and were typicaly 40-60% lower than the cost of new. If your interested in recieving any info.
Electronics Forum | Tue Mar 07 08:48:55 EST 2006 | samir
Our ICT Guy here at my company loves to use lots of via holes as test points - via holes which are 0.040" diameter, and spaced at 0.004" edge to edge spacing! He doesn't like to tent the via's either, so I always battle via-to-via shorts at the wave
Electronics Forum | Fri Feb 06 03:56:47 EST 2004 | JaMi Smith
BGAs and QFPs packaged in Trays are oriented with Pin 1 or corner A1 oriented towards the Pin 1 identifier on one corner of the Tray, which is usually identified by a chamfered corner. The Trays themselves are usually governed by JEDEC Registered Ou
Electronics Forum | Fri Jun 29 14:15:00 EDT 2001 | stefo
This is a question about complying with J-STD-001 solderability testing. Do any of you have your vendors certify that the components and PCB's that you buy from them comply with the solderabilty requirements spelled out in the -002 and -003, in lieu
Electronics Forum | Mon Jul 03 05:39:05 EDT 2006 | ronalds
Hi, I am experience problems while testing wave soldering SMT components that are glued on the solderside (lead free). Between de leads of SOx type IC's and SOT's develop a great deal of solder beads. I have been using a RSS temp.profile while spr
Electronics Forum | Fri Aug 22 15:27:13 EDT 2008 | wayne123
this is the order that I use. 1. Teach pcb origin 2. Teach fiducial location 3. dial in vision on fid in mark info. 4. go into mount and verify that the primary image is on in x/y (after perfoming a teach trace condition) and then do any offsetts if
Electronics Forum | Thu May 13 09:52:34 EDT 2021 | winston_one
Want to update this question a little, I know it appears few years ago, but I hope there is some updates... We have to assembly few samples of motherboards with this kind of finish (customer mistake during pcb order). Normally we can use leaded sold
Electronics Forum | Fri Jun 19 13:40:25 EDT 1998 | Terry Burnette
| Has anyone had experience with placing BGA on gold plated boards. I thought I read a while ago there was a problem with embrittlment causing cracked joints. If anyone has experience with this your feedback would be great. | Mike There has been a
Electronics Forum | Thu Feb 15 13:46:16 EST 2018 | aemery
Griinder, Maybe it's me, but I think what you might be saying here is that you see a reflected image of the PCB or Stencil when you and teaching the fiducials and it is interfering with the teaching routine, is that correct? If this is true it is c
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