Technical Library | 2017-10-05 17:13:04.0
Intermetallic compounds (IMC) in solder bonds are commonly considered critical for the reliability of interconnections. The microstructure and thermal aging characteristics of solder bonds of crystalline silicon solar cells are investigated, whereby two solders, Sn60Pb40 and a lead-free, low melting point alternative Sn41Bi57Ag2 are considered.
Technical Library | 2014-12-11 18:00:09.0
The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Wire bonded packages using conventional copper lead frame have been used in industry for quite some time. However, the demand for consumer electronics is driving the need for flip chip interconnects as these packages shorten the signals, reduce inductance and improve functionality as compared to the wire bonded packages. The flip chip packages have solder bumps as interconnects instead of wire bonds and typically use an interposer or organic substrate instead of a metal lead frame (...) The paper provides a general overview of typical defects and failure modes seen in package assembly and reviews the efforts needed to understand new failure modes during package assembly. The root cause evaluations and lessons learned as the factory transitioned to thin form factor packages are shared
Technical Library | 1999-07-21 09:00:55.0
Isotropic conductive adhesives are typically silver filled epoxy resins. Electronics assemblers have evaluated these materials for a variety of unique interconnect applications. The goal is a conductive polymer that exhibits similar reliability and performance to traditional solder while offering the benefits of a polymer structure such as low temperature processing and good thermal stability as well as the ability to bond a variety of substrates.
Technical Library | 1999-08-05 10:34:17.0
This document defines a set of standard test structures with which to benchmark the electrostatic discharge (ESD) robustness of CMOS technologies. The test structures are intended to be used to evaluate the elements of an integrated circuit in the high current and voltage ranges characteristic of ESD events. Test structures are given for resistors, diodes, MOS devices, interconnects, silicon control rectifiers, and parasitic devices. The document explains the implementation strategy and the method of tabulating ESD robustness for various technologies.
Technical Library | 2007-06-13 13:44:10.0
Very high performance computer applications have created a demand for large organic substrates capable of interconnecting one or a few ASIC semiconductor devices with packaged memory devices. The electrical advantages offered by the use of a thin PTFE composite substrate were coupled with intrinsic mechanical advantages to create very high performance applications. The application development required interactions of design, fabrication, and new manufacturing technology to obtain rapid prototype production and allow a successful ensuing manufacturing ramp.
Technical Library | 2008-01-24 21:42:39.0
Although many through-hole components are being replaced by their surface mount (SMT) counterparts, printed circuit boards (PCBs) are still being designed with both types of components. Often, there are interconnect hardware, displays, or other components that cannot withstand the exposure to the high temperature involved in the wave soldering process. They are generally soldered by hand. The challenge is to determine the optimal method manufacturers can use to solder these boards populated with mixed technology.
Technical Library | 2008-11-06 02:17:59.0
For many years Acoustic Micro Imaging (AMI) techniques have been utilized to evaluate the quality of the underfill used to support the solder bump interconnections of Flip Chip type devices. AMI has been established as one of the few techniques that can provide reliability and quality control data, but little has been done to automate the evaluation process for Flip Chip underfill until now.
Technical Library | 2009-07-22 18:33:41.0
This paper deals with the thermal effects of joule heating in a high interconnect density, thin core, buildup, organic flip chip substrate. The 440 μm thick substrate consists of a 135 μm thick core with via density of about 200 μm. The typical feature sizes in the substrate are 50 micron diameter vias is the core/buildup layers and 12 micron thick metal planes. An experimental test vehicle is powered with current and the temperature rise was measured. A numerical model was used to simulate the temperature rise in the TV.
Technical Library | 2013-01-31 18:43:15.0
There are three key industry trends that are driving the need for temperature-dependent warpage measurement: the trend toward finer-pitch devices, the emergence of lead-free processing, and changes in device form factors. Warpage measurement has become a key measurement for analysis; prevention and prediction of interconnect defects and has been employed in failure analysis labs and production sites worldwide. First published in the 2012 IPC APEX EXPO technical conference proceedings
Technical Library | 2013-03-21 21:24:49.0
This paper explores the behaviour of a copper test vehicle with multiple reflowed solder joints, which has direct relevance to ball grid arrays (BGA) and high density interconnect structures. The paper explores the relative stress conditions on the distributed joints and the sensitivity to ball joint shape... First published in the 2012 IPC APEX EXPO technical conference proceedings
