Electronics Forum | Mon Aug 28 17:54:59 EDT 2000 | Steve Thomas
We're trying out 0603 packages on some 0805 footprints (at this stage only on some test boards) since our vendor tells us the 0805's are going to be getting harder to get, and more expensive to pay for. I understand the IPC footprint for the two is
Electronics Forum | Thu Aug 05 08:39:26 EDT 1999 | Wayne Sanita
| | | Hello, If you are using no-clean and they are entrapped in the flux it is also IPC accepted but i havent found a customer yet who agrees with that. Im sure you have checked your profile. I had the same problem with chip components but after c
Electronics Forum | Thu Aug 05 10:55:09 EDT 1999 | Wolfgang Busko
| | | | | | Hello, | If you are using no-clean and they are entrapped in the flux it is also IPC accepted but i havent found a customer yet who agrees with that. Im sure you have checked your profile. I had the same problem with chip components but
Electronics Forum | Thu Mar 10 09:13:15 EST 2005 | davef
From http://www.IPC.org ... IPC-7351 - Generic Requirements for Surface Mount Land Pattern and Design Standard The successor to the IPC-SM-782A is here! The document covers land pattern design for all types of passive and active components, includ
Electronics Forum | Fri Feb 01 19:07:57 EST 2013 | hegemon
We have had some success in void reduction with LGA by pre-tinning or "bumping" the devices before placement. The extra solder seems to allow a slightly higher standoff, and allows better outgassing, is my guess. A lot more labor , but the results
Electronics Forum | Mon Sep 17 15:27:51 EDT 2001 | jschake
Challenges: The basic defects that impact assembly yield are bridging, satellite solder balls, and opens (i.e. tombstones / draw bridges). There are many variables with the stencil printing process that can impact these; several of them are listed
Electronics Forum | Thu Mar 29 14:55:59 EDT 2007 | HOSS
Hello, I searched the forums and found little specific info on LGAs with interior lands. This is not a QFN with a center pad. This is a multi-row BGA without solderballs. I'm looking for recommendations on PCB land to part land ratio, stencil a
Electronics Forum | Wed Jul 25 10:57:08 EDT 2007 | cecil
Our board layout folks are currently designing a PWB using a 132 QFN. The component is .5mm pitch with .35mm square pads. The component manufacturer recommends the following footprint: .4mm square land .3mm square solder resist 1.why do they spec
Electronics Forum | Thu Aug 05 12:20:06 EDT 1999 | John Thorup
| | | | | | | | | | | | | | | Hello, | | | | If you are using no-clean and they are entrapped in the flux it is also IPC accepted but i havent found a customer yet who agrees with that. Im sure you have checked your profile. I had the same problem
Electronics Forum | Fri May 26 05:54:40 EDT 2000 | Sal
For the past year now we have been printing adhesive with no real problems. Our printing ranges from 0603's to SOIC using a variation of aperture sizes and metal thickness foils. The crucial parameters are : aperture sizes : These obviously depend o
