Electronics Forum | Fri Apr 10 20:27:07 EDT 1998 | Jean-Paul Clech
| I am currently involved in a reliability project related to SMT QFP and TSSOP fine pitch solder joint reliability. I have decided to use a temp chamber for stress testing. Is there a test standard that covers this? I am also a bit unsre as to wheth
Electronics Forum | Wed Apr 05 13:59:56 EDT 2000 | Kal C.
Hi Emmanuel, There is lots of info. in SMTNet archive (I think 98 Sept-Dec). I had a lot of problem with PBGA and certain uBGA with their PCB base material (FR-X) and encapsulant. Wolfgang is correct. We had to reprofile our reflow oven , qualify an
Electronics Forum | Sat Jul 24 00:31:21 EDT 1999 | Scott McKee
| Has anyone ever heard of testing solder paste quality by pasting a board and making a determination of the quality by measuring paste height and width after the board is pasted. Would you consider this a valid test for solder paste testing? | I ag
Electronics Forum | Mon Apr 22 02:48:55 EDT 2002 | ianchan
Hi, a did a study on a FMEA for a government project, and I do not relish going thru that S**T again! Aye laddie, as a QA skirt i must protest! its called a kilt, not a skirt! *grinz* and we dun keep FMEAs in the folder cabinet, there's only room f
Electronics Forum | Mon Jan 13 18:22:55 EST 2003 | davef
100 sec) and decrease reflow temp to 205C. * Understand that voids are primarily process indicators. There is experimental evidence that voids retard crack propagation locally around the void on a temporary basis. There is no standard, IPC or otherw
Electronics Forum | Thu Feb 23 10:49:38 EST 2006 | slthomas
Defining failure modes will help determine what you need to quantify in all processes. Personally I wouldn't pursue the DoE angle (varying setup parameters to determine robustness). 1)How about % pad coverage, paste thickness, and accuracy? Define w
Electronics Forum | Mon Jul 24 13:45:14 EDT 2006 | samir
Most Test Technicians, Managers, and everyone else in the organization always believe that the BGA is the #1, and most likely failure mode in a circuit. You can analyze it with all the tools available...2D, 3D, 10D, underneath, etc...... convince th
Electronics Forum | Sat Aug 22 05:19:42 EDT 2009 | ghepo
Dear Eric, in my opinion this is a very complex problem, that require to know many details for answer. For example : 1) what about the PCB finishing ? Have you verify the quality of they ? 2) what about the solder paste (the exactly composition)? 3)
Electronics Forum | Wed Aug 26 05:24:42 EDT 2009 | ghepo
Ok Eric, finally we know that the problem should be the PILLOW (sincerely, your photo is not very clear) and not the crack of the joint. There is a big difference on the failure mode of the two defects... If the problem is realy a pillow I only ca
Electronics Forum | Fri Apr 03 08:34:54 EDT 2020 | SMTA-Gregory
We need to be careful with product to avoid introducing a new failure mode, namely corrosion and dendrite growth, especially those running no clean processes! In addition to heat (reflow, wave and some selective soldering processes) killing the vi
