Electronics Forum: mismatch (Page 5 of 12)

lead free and tombstoning

Electronics Forum | Fri Feb 17 11:01:47 EST 2006 | amol_kane

with lead-free solders, one would expect to find less instances of tombstoning. this is because SAC alloys are not eutectic and melt over a range of temp (usually 217-220 deg C) instead of at a single temperature. therefore the forces due to solder s

Fillet Tearing

Electronics Forum | Wed Mar 22 21:27:45 EST 2006 | KEN

Find out the lead frame alloy. Cte mismatch can cause the same defect. Ran into this 3 years ago wave soldering with Tin-Copper.....okay, you caught me. I admit it. Wavemaster larry told me about this and I'm posting it under my name. Shameful, I

Cleaning under LCC's

Electronics Forum | Wed Oct 11 15:40:34 EDT 2006 | Steve Gregory

Don't think there's any easy way to clean under a LCC, but you might want to consider this: http://www.winslowautomation.com/ccmd.asp A dead simple way to mount solder columns onto LCC's and then solder the part to the PCB with a stand-off of abou

detecting BGA micro cracks

Electronics Forum | Thu Feb 11 08:14:41 EST 2010 | scottp

It's OK to have the daisychain done in the interposer rather than the die (and a lot cheaper) but in thermal cycling the parts MUST have representative die. That's where a large part of the CTE mismatch comes from to cause fatigue damage. Thermal c

ap25 hie

Electronics Forum | Sat Oct 15 19:18:14 EDT 2011 | enttec

Hi Does anyone have a calibration manual for a MPM AP25-Hie ? Have noticed recently that we have a slight mismatch between board and stencil when printing. I have the user manual but we didn't get calibration when we bought this machine Thanks Nic

BGA rework: Coplanarity of Xilinx before and after reflow.

Electronics Forum | Mon May 16 22:59:40 EDT 2005 | davef

We believe your problem is caused by the mismatch in CTE of the material ised in your BGA. In fact, this "potato chipping" [where the corners curl-up] is present in all BGA. The issue is the matter of degree. [Mismatching CTE is how old thermostats

Re: CBGA CTE Mismatch

Electronics Forum | Mon Aug 21 20:20:18 EDT 2000 | Dave F

Hi CJ: I guarantee you that the portions of you BGA that will physically move the most as a result of changing temperature are the corners. For this very reason, many BGA have BT substrates that have a tg of 210�C. I would demonstrate the potentia

Re: Solder Connection Environmental Screening

Electronics Forum | Wed Aug 23 16:18:47 EDT 2000 | Dr. Ning-Cheng Lee

I presume you are referring to vibration test with fixed frequency at room temperature. One procedure describing the detailed profile is in MIL-STD-883E, Method 2005.2 (12/31/96). The approximate profile can be described as 60Hz, 20-70g, and 96 hrs t

Conductor width tolerances

Electronics Forum | Tue Nov 09 05:14:49 EST 1999 | Wolfgang Busko

Hi all, our problem we face is the mismatch of conductor width on the delivered PCB and the nominal width given by CAD-data. With CAD we are improving pads and conductors to match the specific needs for soldering and the board houses counteract our i

Help-Wire Bonding Defects Analysis After Encapsulation

Electronics Forum | Thu Nov 26 03:59:50 EST 1998 | Chi-Ting Chen

I have some 1.25 mils Al wire bonding chip on board process. After epxoy-based encapsulation, I do some aging test. How can I "see" or prove that there is a "wire break" exist due to the tension of thermal cycling? How can I know the failure is cause

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