Technical Library: .012 (Page 6 of 7)

Drop Impact Reliability of Edge-bonded Lead-free Chipscale Packages

Technical Library | 2010-03-30 21:51:23.0

This paper presents the drop test reliability results for edge-bonded 0.5mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board.

Flex (Flextronics International)

Flexible Hybrid Circuit Fully Inkjet-Printed: Surface Mount Devices Assembled By Silver Nanoparticles-Based Inkjet Ink

Technical Library | 2018-06-27 16:47:13.0

Nowadays, inkjet-printed devices such as transistors are still unstable in air and have poor performances. Moreover, the present electronics applications require a high degree of reliability and quality of their properties. In order to accomplish these application requirements, hybrid electronics is fulfilled by combining the advantages of the printing technologies with the surface-mount technology. In this work, silver nanoparticle-based inkjet ink (AgNP ink) is used as a novel approach to connect surface-mount devices (SMDs) onto inkjet-printed pads, conducted by inkjet printing technology

Universitat de Barcelona

A New Line Balancing Method Considering Robot Count and Operational Costs in Electronics Assembly

Technical Library | 2019-05-02 13:47:39.0

Automating electronics assembly is complex because many devices are not manufactured on a scale that justifies the cost of setting up robotic systems, which need frequent readjustments as models change. Moreover, robots are only appropriate for a limited part of assembly because small, intricate devices are particularly difficult for them to assemble. Therefore, assembly line designers must minimize operational and readjustment costs by determining the optimal assignment of tasks and resources for workstations. Several research studies address task assignment issues, most of them dealing with robot costs as fixed amount, ignoring operational costs. In real factories, the cost of human resources is constant, whereas robot costs increase with uptime. Thus, human workload must be as large and robot workload as small as possible for the given number of humans and robots. We propose a new task assignment method that establishes a workload balancing that meet precedence and further constraints.

Fujitsu Laboratories Ltd.

Accurate Quantitative Physics-of-Failure Approach to Integrated Circuit Reliability

Technical Library | 2011-06-02 15:49:09.0

Modern electronics typically consist of microprocessors and other complex integrated circuits (ICs) such as FPGAs, ADCs, and memory. They are susceptible to electrical, mechanical and thermal modes of failure like other components on a printed circuit boa

DfR Solutions

Inclusion Voiding in Gull Wing Solder Joints

Technical Library | 2012-08-30 21:24:29.0

This paper provides definitions of the different voiding types encountered in Gull Wing solder joint geometries. It further provides corresponding reliability data that support some level of inclusion voiding in these solder joints and identifies the final criteria being applied for certain IBM Server applications. Such acceptance criteria can be applied using various available x-ray inspection techniques on a production or sample basis. The bulk of supporting data to date has been gathered through RoHS server exempt SnPb eutectic soldering operations but it is expected to provide a reasonable baseline for pending Pb-free solder applications.

IBM Corporation

Microspring Characterization and Flip-Chip Assembly Reliability

Technical Library | 2014-05-29 13:48:14.0

Electronics packaging based on stress-engineered spring interconnects has the potential to enable integrated IC testing, fine pitch, and compliance not readily available with other technologies. We describe new spring contacts which simultaneously achieve low resistance ( 30 μm) in dense 2-D arrays (180 ~ 180-µm pitch). Mechanical characterization shows that individual springs operate at approximately 150-µN force. Electrical measurements and simulations imply that the interface contact resistance contribution to a single contact resistance is This paper suggests that integrated testing and packaging can be performed with the springs, enabling new capabilities for markets such as multichip modules.

Institute of Electrical and Electronics Engineers (IEEE)

Evaluating Automated Wafer Measurement Instruments

Technical Library | 1999-08-05 09:34:44.0

This document demonstrates a sequential process of evaluating automated wafer instruments and discusses why this approach is useful for studying instruments that have automation features such as loading and focusing mechanisms. The methodology specifies a series of experiments consisting of two or more capability studies followed by a stability study. Each experiment achieves a separate goal, yet combines with the others in providing information needed to assess the usefulness of the instrument.


A Novel Local Search Integer-Programming-Based Heuristic for PCB Assembly on Collect-and-Place Machines

Technical Library | 2011-11-03 18:04:07.0

This paper presents the development of a novel vehicle-routing-based algorithm for optimizing component pick-up and placement on a collect-and-place type machine in printed circuit board manufacturing. We present a two-phase heuristic that produces soluti

Mechanical Science and Engineering at UIUC

Electromigration Damage Mechanics of Lead-Free Solder Joints Under Pulsed DC: A Computational Model

Technical Library | 2013-06-13 15:31:24.0

Electromigration (EM) is a mass transportation mechanism driven by electron wind force, thermal gradient, chemical potential and stress gradient. According to Moore’s law, number of transistors on integrated circuits (ICs) doubles approximately every 2 years. Moore’s law holds true since its introduction in 1970s. This insatiable demand for smaller ICs size, larger integration and higher Input/Output (IO) count of microelectronics has made ball grid array (BGA) the most promising connection type in electronic packaging industry. This trend, however, renders EM reliability of solders joints a major bottleneck to hinder further development of electronics industry...

Electronic Packaging Laboratory, State University of New York

Status and Outlooks of Flip Chip Technology

Technical Library | 2018-11-14 21:43:14.0

Status of flip chip technology such as wafer bumping, package substrate, flip chip assembly, and underfill will be reviewed in this study. Emphasis is placed on the latest developments of these areas in the past few years. Their future trends will also be recommended. Finally, the competition on flip chip technology will be briefly mentioned.

ASM Pacific Technology

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