Electronics Forum | Fri Sep 12 15:32:32 EDT 2003 | Mark Pilkington
EPTAC Corporation provides training and certification to all IPC industry standards. We can be reached at 800.643.7822 and our site is http://www.eptac.com.
Electronics Forum | Tue Nov 18 18:25:57 EST 2003 | Gabriele
To process Multy Layer Ceramic Chip Capacitor is a critical process some time underevaluated mainly at rework or repair step. You can find useful guidelines on J-STD-001 G
Electronics Forum | Tue Nov 25 17:43:09 EST 2003 | Gabriele
Try to see J-STD-001 Chapter 8.Cleaniness Requirements. Also you could info also on ASTM D5127-99. Rgds
Electronics Forum | Wed Mar 03 05:38:23 EST 2004 | Gabriele
In addition to the already helpful J-STD-001C,you can find other details also on Standard :IEC-61192-1 "Workmanship Requirements for Electronic Assemblies" Regards GLS
Electronics Forum | Fri Mar 19 09:48:02 EST 2004 | Patticake
I have a similar question. What are the major differences between J-std-001 and IPC 610 class 3 ?
Electronics Forum | Tue Nov 07 07:55:43 EST 2006 | davef
We use J-STD-001, a widely accepted consensus document, control limits of 18-30*C, 30-70%RH. Search the fine SMTnet Archives for background.
Electronics Forum | Fri Jan 12 11:18:09 EST 2007 | kglidden
J-STD-001 makes RECOMMENDATIONS but they are not REQUIREMENTS. Only REQUIREMENT is to make sure your ESD control is adequate if RH falls below 30%.
Electronics Forum | Wed Jul 11 14:44:21 EDT 2007 | fredericksr
Hi folks! Has anyone ever successfully verified adequate ESD control at
Electronics Forum | Wed Dec 12 21:43:16 EST 2007 | davef
There is no specification for solder paste height, just as there is no specification for paste volume. Focus on producing a fillet that meets J-STD-001. You make the choices that produce the end result.
Electronics Forum | Mon Aug 04 14:54:09 EDT 2008 | blnorman
J-STD-001 Table 5-1 lists the allowable impurity levels for SnPb wave solder pots.
