Technical Library: high mix (Page 7 of 30)

Improve Crimp Quality to Increase Productivity

Technical Library | 2015-08-17 09:07:11.0

Since a high percentage of product failures can be traced to poor electrical connections, crimp quality is of paramount importance. There are many factors that come into play that affect crimp quality and knowing the relevant factors, and to what extent each factor affects the end result, will help to guide the process engineer towards achieving the best possible results.

Schleuniger, Inc.

Vapor Phase Technology and its Application

Technical Library | 2013-03-27 23:43:40.0

Vapor phase, once cast to the annals’ of history is making a comeback. Why? Reflow technology is well developed and has served the industry for many years, it is simple and it is consistent. All points are true – when dealing with the centre section of the bell curve. Today’s PCB manufacturers are faced with many designs which no longer fall into that polite category but rather test the process engineering groups with heavier and larger panels, large ground planes located in tricky places, component mass densities which are poorly distributed, ever changing Pb Free alloys and higher process temperatures. All the time the costs for the panels increase, availability of “process trial” boards diminishes and yields are expected to be extremely high with zero scrap rates. The final process in the assembly line has the capacity to secure all the value of the assembly or destroy it. If a panel is poorly soldered due to poor Oven setup or incorrect programming of the profile the recovery of the panel is at best expensive, at worst a loss. For these challenges people are turning to Vapor Phase.

A-Tek Systems Group LLC

Startling Results From Reliability Testing

Technical Library | 2009-03-13 00:27:09.0

Open product reliability testing in Stockholm, Sweden in January as part of a live production event generated some quite startling results. It was apparent that many components simply cannot handle the high reflow temperatures of a lead-free soldering process, and that many surface-mount machine suppliers are battling significant problems with QFN packages and other components that are mounting edgeways (bill boarding). However, some suppliers have achieved good results.

Mycronic Technologies AB

Best Practices in Selecting Coatings and Pottings for Solar Panel Systems; Junction Boxes and Inverters

Technical Library | 2020-08-13 01:12:57.0

The solar industry has driven solutions that result in electronics systems that are required to perform in outside environments for over 25 years. This industry expectation has resulted in solutions to protect the electronics from failure that can result from interaction with moisture, and various chemicals leading to corrosion and shorting of the systems. Potting and encapsulation compounds can impart the very high level of protection from environmental, thermal, chemical, mechanical, and electrical conditions that the solar applications demand.

DfR Solutions

Transient Solder Separation of BGA Solder Joint During Second Reflow Cycle

Technical Library | 2019-05-15 22:26:02.0

As the demand for higher routing density and transfer speed increases, Via-In-Pad Plated Over (VIPPO) has become more common on high-end telecommunications products. The interactions of VIPPO with other features used on a PCB such as the traditional dog-bone pad design could induce solder joints to separate during the second and thereafter reflows. The failure has been successfully reproduced, and the typical failure signature of a joint separation has been summarized.To better understand the solder separation mechanism, this study focuses on designing a test vehicle to address the following three perspectives: PCB material properties, specifically the Z-direction or out-of-plane Coefficient of Thermal Expansion (CTE); PCB thickness and back drill depth; and quantification of the driving force magnitude beyond which the separation is due to occur.

Cisco Systems, Inc.

Boundary Scan Advanced Diagnostic Methods

Technical Library | 2013-02-14 12:54:29.0

Boundary-scan (1149.1) technology was originally developed to provide a far easier method to perform digital DC testing to detect intra-IC interconnect assembly faults, such as solder shorts and opens. Today's advanced IC technology now includes high-speed differential interfaces that include AC or DC coupling components loaded on the printed circuit assembly. Simple stuck-at-high/low test methods are not sufficient to detect all assembly fault conditions, which includes shorts, opens and missing components. Improved diagnostics requires detailed circuit analysis, predictive assembly fault simulation and more complex testing to isolate and accurately detect all possible assembly faults... First published in the 2012 IPC APEX EXPO technical conference proceedings

Agilent Technologies, Inc.

Development of Halogen Free, Low Loss Copper-Clad Laminates Containing a Novel Phosphonate Oligomer

Technical Library | 2017-08-24 16:53:20.0

With the rapid development of the information industry, increasing attention is being paid to the dielectric performance of base materials including copper-clad laminates (CCL) and prepregs. In addition to the increasingly high performance requirements of CCL's, the present global attention to less toxic products is leading to an increase in the use of halogen-free flame retardants in electronics. (...) This paper introduces a new phosphonate oligomer which can be used as a reactive flame retardant in epoxy based resin systems. Suitable conditions for the complete reaction between the phosphonate oligomer and epoxy resin are described and the resulting halogen-free laminates with improved properties such as low Df, low coefficient of thermal expansion (CTE), high peel strength, and good toughness are presented.

FRX Polymers Inc.

VOC-Free Wave Solder Flux Evaluation

Technical Library | 1999-04-26 15:51:30.0

The goal of the flux evaluation was to identify one product that would meet the needs of all SICN's wave solder products and processes while producing high quality assemblies. At the outset of the evaluation, it was unclear whether a single flux chemistry could satisfy such a broad range of demands, particularly because SICN's utilization of less aggressive, low-impact chemicals.

Siemens Process Industries and Drives

Resin Coated Copper Capacitive (RC3) Nanocomposites for System in a Package (SiP): Development of 3-8-3 structure

Technical Library | 2009-10-08 01:58:04.0

In the present study, we report novel ferroelectric-epoxy based polymer nanocomposites that have the potential to surpass conventional composites to produce thin film capacitors over large surface areas, having high capacitance density and low loss. Specifically, novel crack resistant and easy to handle Resin Coated Copper Capacitive (RC3) nanocomposites capable of providing bulk decoupling capacitance for a conventional power-power core, or for a three layer Voltage-Ground-Voltage type power core, is described.

i3 Electronics

Semi-Additive Process (SAP) Utilizing Very Uniform Ultrathin Copper by A Novel Catalyst

Technical Library | 2020-09-02 22:14:36.0

The demand for miniaturization and higher density electronic products has continued steadily for years, and this trend is expected to continue, according to various semiconductor technology and applications roadmaps. The printed circuit board (PCB) must support this trend as the central interconnection of the system. There are several options for fine line circuitry. A typical fine line circuit PCB product using copper foil technology, such as the modified semi-additive process (mSAP), uses a thin base copper layer made by pre-etching. The ultrathin copper foil process (SAP with ultrathin copper foil) is facing a technology limit for the miniaturization due to copper roughness and thickness control. The SAP process using sputtered copper is a solution, but the sputtering process is expensive and has issues with via plating. SAP using electroless copper deposition is another solution, but the process involved is challenged to achieve adequate adhesion and insulation between fine-pitch circuitries. A novel catalyst system--liquid metal ink (LMI)--has been developed that avoids these concerns and promotes a very controlled copper thickness over the substrate, targeting next generation high density interconnect (HDI) to wafer-level packaging substrates and enabling 5-micron level feature sizes. This novel catalyst has a unique feature, high density, and atomic-level deposition. Whereas conventional tin-palladium catalyst systems provide sporadic coverage over the substrate surface, the deposited catalyst covers the entire substrate surface. As a result, the catalyst enables improved uniformity of the copper deposition starting from the initial stage while providing higher adhesion and higher insulation resistance compared to the traditional catalysts used in SAP processes. This article discusses this new catalyst process, which both proposes a typical SAP process using the new catalyst and demonstrates the reliability improvements through a comparison between a new SAP PCB process and a conventional SAP PCB process.

Averatek Corporation


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