Technical Library | 2007-01-31 12:08:36.0
Air-powered dispensing systems use controlled pulses of air pressure to dispense solder paste from syringe reservoirs in uniform amounts. In this paper, EFD explains the most critical variables affecting air-powered dispensing of solder pastes and shows how to manage those variables to your advantage.
Technical Library | 2013-03-27 23:43:40.0
Vapor phase, once cast to the annals’ of history is making a comeback. Why? Reflow technology is well developed and has served the industry for many years, it is simple and it is consistent. All points are true – when dealing with the centre section of the bell curve. Today’s PCB manufacturers are faced with many designs which no longer fall into that polite category but rather test the process engineering groups with heavier and larger panels, large ground planes located in tricky places, component mass densities which are poorly distributed, ever changing Pb Free alloys and higher process temperatures. All the time the costs for the panels increase, availability of “process trial” boards diminishes and yields are expected to be extremely high with zero scrap rates. The final process in the assembly line has the capacity to secure all the value of the assembly or destroy it. If a panel is poorly soldered due to poor Oven setup or incorrect programming of the profile the recovery of the panel is at best expensive, at worst a loss. For these challenges people are turning to Vapor Phase.
Technical Library | 2014-01-30 18:08:04.0
As of today, the electronic industry is aware of the requirements for their products to be lead free. All components are typically available in lead free quality. This comprises packages like BGAs with BGA solder balls to PCB board finishes like HASL. The suppliers are providing everything that is needed. It is harder to get the old tin leaded (SnPb) components for new applications today, than lead free ones. So why has not everybody changed over fully yet and how can the challenges be overcome? A big concern in this transition process is reflow soldering. The process temperatures for lead free applications became much higher. Related with this is more stress for all the components. It affects the quality and reliability of the electronic units and products...
Technical Library | 2007-06-13 13:44:10.0
Very high performance computer applications have created a demand for large organic substrates capable of interconnecting one or a few ASIC semiconductor devices with packaged memory devices. The electrical advantages offered by the use of a thin PTFE composite substrate were coupled with intrinsic mechanical advantages to create very high performance applications. The application development required interactions of design, fabrication, and new manufacturing technology to obtain rapid prototype production and allow a successful ensuing manufacturing ramp.
Technical Library | 2014-07-10 17:37:18.0
This paper studies and compares the effects of pull–pull and 3-point bending cyclic loadings on the mechanical fatigue damage behaviors of a solder joint in a surface-mount electronic package.The comparisons are based on experimental investigations using scanning electron microscopy (SEM) in-situ technology and nonlinear finite element modeling, respectively. The compared results indicate that there are different threshold levels of plastic strain for the initial damage of solder joints under two cyclic applied loads; meanwhile, fatigue crack initiation occurs at different locations, and the accumulation of equivalent plastic strain determines the trend and direction of fatigue crack propagation. In addition, simulation results of the fatigue damage process of solder joints considering a constitutive model of damage initiation criteria for ductile materials and damage evolution based on accumulating inelastic hysteresis energy are identical to the experimental results. The actual fatigue life of the solder joint is almost the same and demonstrates that the FE modeling used in this study can provide an accurate prediction of solder joint fatigue failure.
Technical Library | 2017-07-06 15:50:17.0
Head-in-pillow (HiP) is a BGA defect which happens when solder balls and paste can't contact well during reflow soldering. Package warpage was one of the major reasons for HiP formation. In this paper, package warpage was measured and simulated. It was found that the package warpage was sensitive to the thickness of inside chips. A FEM method considering viscoelastic property of mold compound was introduced to simulate package warpage. The CTE mismatch was found contributes to more than 90% of the package warpage value when reflowing at the peak temperature. A method was introduced to measure the warpage threshold, which is the smallest warpage value that may lead to HiP. The results in different atmospheres showed that the warpage threshold was 50μm larger in N2 than that in air, suggesting that under N2 atmosphere the process window for HiP defects was larger than that under air, which agreed with the experiments.
Technical Library | 2009-12-03 14:27:29.0
This paper provides additional data in support of shelf life extension for BGA and Die Size BGA (DSBGA) Packages.
Technical Library | 2011-08-04 19:29:53.0
This work covers two major projects aimed at increasing quality and efficiency on a high mix, low volume surface mount electronics production line. Specifically the installation of a ten zone reflow oven and an enhanced changeover method for SMT pick and
Technical Library | 1999-07-21 08:49:49.0
As the role of direct-chip-attachment increases in the electronics industry, the reliability and performance of COB packaging materials becomes an increasing concern. Although many factors influence component reliability, the biggest determinants of performance are often the glass transition temperature (Tg) and the coefficient of thermal expansion (CTE) of the encapsulant or underfill. This paper discusses exactly what these properties are, how they are measured, and why they are important to device-reliability.
Technical Library | 2003-05-05 07:36:58.0
The stencil selection process can be confusing, particularly when creating a stencil for a new application. This tutorial, which covers stencils for SMT and advanced IC packaging applications, offers guidelines to assist users in stencil selection and print optimization.