Electronics Forum | Tue Oct 05 20:07:12 EDT 2004 | davef
We do not know how your KIC2000 calculates slope. Here's an approach to calculating slope: * Subtract the lower temperature from the upper temperature. [Temp|upper-Temp|lower] = Temp|change * Subtract the time when the lower temperature was measured
Electronics Forum | Mon Jan 10 22:43:43 EST 2005 | davef
First, we know nothing about your assemblies or how storing them in an "unconditioned" warehouse will affect their performance or post-storage processing. Second, there are no specifications, because what might be good in one application might not b
Electronics Forum | Tue Feb 07 05:40:16 EST 2006 | pavel_murtishev
Good day, J-STD-033A: 4.1.2.2 Moisture Sensitivity Levels 5-5a For moisture sensitivity Levels 5 and 5a with floor life exposure not greater than 8 hours, a minimum desiccating period of 10X the exposure time is required to dry the SMD packages en
Electronics Forum | Wed Aug 09 08:06:07 EDT 2006 | davef
See "IPC-4554 Specification for Immersion Tin Plating for Printed Circuit Boards" 3.2.1 Immersion Tin Thickness. The most common reason for solderability issues with the white tin surface coating during multiple thermal excursions is a thin white ti
Electronics Forum | Thu Nov 02 15:46:43 EST 2006 | rgduval
I'm looking for some information on soldering irons being used in my no-lead process. Specifically, my floor seem to be burning out tips at an alarming rate, when soldering lead-free assemblies. Today, I had one woman burn out a brand new tip in 4
Electronics Forum | Wed Dec 19 20:42:55 EST 2007 | davef
gersla: You're correct that carriers of low temperature material will disfigure and become useless at 125*C bake temperatures. The reason you can not find 70*C bake data is: J-STD033B, "4.2.2 Low Temperature Carriers. SMD packages shipped in low tem
Electronics Forum | Mon Jan 14 22:52:48 EST 2008 | davef
Using larger pads on the corners is fairly common to improve self-alignment of BGA and CSP. For example, "9.3.2.8 Large corner pads and overprint The self-alignment of BGA or CSP can be improved through a design change. By utilizing a large board pad
Electronics Forum | Mon Jun 30 08:55:31 EDT 2008 | davef
It will be tough to find a dimensional thickness specification for HASL. IPC-6012 Table 3-2, line "Fused tin-lead or solder coat - Coverage and Solderable" states the requirement that there has to be complete coverage of solder on the land, and it mu
Electronics Forum | Wed Jul 23 03:04:57 EDT 2008 | gfro
Hello, We are using a PCB with thickness 3.2mm 4 layer and lot of through hole via's of diameter 0.4mm. We specified our PCB vendor to do plugging. Now we have big problems, that after 1..4 weeks we measure a low resistance between track's/via's of
Electronics Forum | Wed Jul 23 08:18:29 EDT 2008 | davef
Q1. Is this a standard process for plugging? A1. Not as such. We checked both IPC-6012 and IPC-SM-840. Neither comments on plugging. So, your fabrication notes rule the day. Q2. Is this okay for such thick PCB's or is it mandatory to use a special pl
