Electronics Forum: planarization (Page 8 of 12)

In AOI, 3D v.s. 2D imaging?

Electronics Forum | Mon May 07 09:47:45 EDT 2001 | orbotech

An ultimate truth in AOI is that "you can not avoid what you can not see". At the post solder stage, 2D inspection is typically not enough as it simply "can not see" everything using a single perspective, and therefore, can not detect all of the faul

Re: D-Pak misalignment Problem

Electronics Forum | Sat Dec 04 09:23:20 EST 1999 | Christopher Lampron

Kantesh, Does this particular part have a heat sink across the bottom side of the component and does your pad size and stencil aperture match the component? I have just had a very similar problem with a DPAK. What we found was that the recomended pad

Detecting lifted leads on QFPs

Electronics Forum | Fri May 28 07:37:52 EDT 1999 | Steve Cheung

Yes l know this problem keeps cropping up on the forum but l've missed some of the follow-ups. Our problem is that the lifting only occurs on 3% of production so actually detecting an improvement is difficult. We're actually having to inspect 144 p

Re: Cleaning procedures for Entek-Plus Cu-106A

Electronics Forum | Mon Apr 26 11:04:53 EDT 1999 | Dave F

| | Earl said, in essence: | | | | | Justin is absolutely right ... | | | | | | Again, Entek is not much more than a flux coating ... | | | | | | Metallic coatings protect best, as we all know - especially those electroplated. Those coatings chemi

Re: Humidity bake bends leads

Electronics Forum | Fri Apr 16 19:52:39 EDT 1999 | Scott McKee

| While trying to sell me a low temperature baking system for SMDs the salesman mentioned that the 125C for 24hr bake had been known to cause co-planarity defects. | I thought I'd ask some experts. Any help guys? | Let me get this straight... He's

Re: Squeegee Pressure

Electronics Forum | Tue Feb 16 08:54:57 EST 1999 | Ross Berntson

| I am fairly new to the SMT game and I am getting conflicting answers to the following. Maybe someone can help me! When printing, one person is telling me that the stencil should be wiped completely clean of all paste because the quality of the

Paste / Flux during rework?

Electronics Forum | Mon Aug 12 12:05:35 EDT 2002 | russ

I use Paste for high temp balls and/or co-planarity/warpage issues. normally I only use paste flux for ball attachment. One down side to paste application is registration and volume anomalies with those little micro-stencils (for me anyway). Your

No-Lead solder defect - No solder on pads

Electronics Forum | Fri Dec 12 11:52:59 EST 2003 | Marc Simmel

I have encountered problems with a 90/10 tin-lead plated SMT component wicking all the solder paste off the pads on the substrate. Worst, the defect occurs randomly - adjacent leads may have 'good' joints, though heel fillets are poor. The solder pa

QFP soldering issue

Electronics Forum | Wed Jan 14 10:07:38 EST 2004 | Patrick

More on QFP soldering issue as per Paul f original e-mail. 1. Problems occured on different PCB's, on different lines using different equipment 2. Flux residue is common in the dimple on the solder. 3. The fault occurred using both "Kester 265" & "Al

Solder paste height checking

Electronics Forum | Mon Feb 21 03:51:37 EST 2005 | abhirami

Solder paste thickness control is more important in SMT process. What controls do you have? I guess if everyone follows the critical control path, then there are always reduced problems. The issue is no one is perfect. Paste tends to be on the stenci


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