Electronics Forum: pad definition (Page 9 of 14)

Re: Electropolishing Laser-Cut Stencils

Electronics Forum | Wed Jul 15 12:22:57 EDT 1998 | Steve Moore

Electropolishing definitely improves the print characteristics of both Laser-cut and Chem-etch stencils. The caveat here is avoid over polishing which results in rounding of the edges and/or enlargement of the openings. Over polishing is typically th

CLEANING OXIDIZATION OFF OF WHITE TIN PADS

Electronics Forum | Fri Jul 18 10:46:43 EDT 2003 | davef

If you are saying that you have discolored white tin at in-bound inspection, you have bad boards. The boards are fabricated incorrectly. Your fabricator is deficient. That is the GREAT thing about imm coatings. You can look at them and determine

Solder Wetting Problems, Need Referee's

Electronics Forum | Tue May 31 11:56:12 EDT 2005 | chunks

Hi Matt, Get definitive answers! Contamination on the HASL finish?: From the pix you posted, it looks like something fishy is going on. I�d reject them back to the board house and demand an answer. Most board houses and purchasing people will g

Ag/Pd termination, reflow soldering issues

Electronics Forum | Wed Apr 04 03:07:16 EDT 2007 | pavel_murtishev

Good morning, Problem definition Poor soldering of thermistors with Ag/Pd termination Background Process: lead free reflow soldering Paste type: Multicore LF300, SAC305 Component type: 0805 chip thermistor, Ag/Pd termination PWB finish: immersion A

Reflow Profile Design

Electronics Forum | Fri Jun 15 12:08:49 EDT 2007 | ck_the_flip

Hi Grant, 1st off solder paste data sheets are just "guidelines". You always need to set your specs. based on the needs of your own process and product. Don't ever follow your solder-paste data sheet to the tee, or you're severely limiting yoursel

PC Board Guidelines

Electronics Forum | Thu Sep 20 16:06:23 EDT 2007 | jmelson

Are these shorts occuring after reflow, or are they shorted on the incoming boards before stuffing? If the latter, is the fabricator doing electrical test? How are these boards getting past their electrical test? Especially if multilayer, there's

Standard for automated placement & assembly, density etc.

Electronics Forum | Sat Feb 18 09:20:09 EST 2012 | davef

The 3-Tier PCB library concept was originally created by IEC (International Electromechanical Commission) in 1999 and introduced to IPC in 2000. The concept had to be created as a solution for high density packaging for hand held devices to ruggedize

Re: Aperture Reduction for QFP (fine pitch)

Electronics Forum | Tue Sep 21 09:33:30 EDT 1999 | Scott Davies

| | | My stencil thickness is 6 mil and we got qfp's with fine pitch. | | | how many percent should i reduce my stencil aperture using a 6 mil stencil for 0.5 mm pitch and 0.4 mm pitch ? | | | | | | thanks | | | | | We use 6 mil lasercut stencils w

Re: Cylindrical diodes Missing during SMT process.

Electronics Forum | Tue Aug 24 06:40:18 EDT 1999 | Gyver

| | | Hello everyone, | | | We found many cylindrical diodes missing during SMT process. Could someone tell us how to prevent this problem? Is it effective to change the shape of stencil apture or reduce fan speed in reflow oven? Thanks in advance. |

Re: Cylindrical diodes Missing during SMT process.

Electronics Forum | Tue Aug 24 11:36:37 EDT 1999 | Jimmy G

| | | | Hello everyone, | | | | We found many cylindrical diodes missing during SMT process. Could someone tell us how to prevent this problem? Is it effective to change the shape of stencil apture or reduce fan speed in reflow oven? Thanks in advanc


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