Technical Library: packing (Page 10 of 16)

Criminal Prosecution - Who can be held liable for the sale of counterfeit parts?

Technical Library | 2011-09-26 13:53:30.0

On September 14, 2010, the late Shannon Wren, owner of VisionTech Components ("VisionTech"), and Stephanie McCloskey, VisionTech's Administrative Manager, were arrested during the execution of search and seizure warrants issued against the pair by the United States government after evidence connected them to the sale of counterfeit parts to the U.S. Navy, defense contractors and others. A ten-count indictment charged McCloskey with conspiracy, aiding and abetting in violation of Title 18 United States Code, Sections 371 and 2; trafficking in counterfeit goods, in violation of Title 18 United States Code, Section 2320; and mail fraud, in violation of Title 18 United States Code, Section 1341. McCloskey pled guilty to conspiracy and aiding and abetting for her role in the scheme.

ERAI Inc.

Minimizing Voiding In QFN Packages Using Solder Preforms

Technical Library | 2012-07-27 11:18:29.0

First published in the 2012 IPC APEX EXPO technical conference proceedings. The focus of this paper will quantify the preform requirements and process adjustments needed to use preforms in a standard SMT process. In addition, experimental data showing vo

Indium Corporation

Best Practices Reflow Profiling for Lead-Free SMT Assembly

Technical Library | 2013-06-05 23:14:44.0

The combination of higher lead-free process temperatures, smaller print deposits, and temperature restraints on electrical components has created difficult challenges in optimizing the reflow process. Not only are the electronic components and the PWB at risk, but the ability to achieve a robust solder joint becomes difficult, especially if the PCB is thermally massive. In addition, the constant miniaturization of electronic components, hence smaller solder paste deposits, may require the use of smaller particle-sized powders (...) This paper is a summary of best practices in optimizing the reflow process to meet these challenges of higher reflow temperatures, smaller print deposits, decreased powder particle size, and their affect on the reflow process.

Indium Corporation

Stencil Design Guidelines for Electronics Assembly Technologies.

Technical Library | 2014-03-13 15:25:01.0

A student competition paper at Budapest University of Technology And Economics, Department of Electronics Technology gives background, covers stencil design and discusses stencils intended for pin in paste application. The stencil applied for depositing the solder paste is a thin, 75–200 µm thick metal foil, on which apertures are formed according to the solder pads on the printed circuit board. Stencil printing provides a fast, mass solder paste deposition process; relatively expensive, appropriate and recommended for mass production.

Budapest University of Technology and Economics

Today's Vapor Phase Soldering An Optimized Reflow Technology for Lead Free Soldering

Technical Library | 2014-03-20 12:37:39.0

In the beginning of SMT, Vapor Phase Soldering was the preferred reflow soldering technology because of its excellent heat transfer capabilities. There were also some disadvantages like fast temperature rise, nearly no influence on the temperature profiles and high costs. So the use of Vapor Phase Soldering was reduced to special applications with high mass or complex boards in low numbers (e.g. for military or aerospace use).

IBL - Löttechnik GmbH

Ready to Start Measuring PCB Warpage during Reflow? Why and How to Use the New IPC-9641 Standard

Technical Library | 2014-08-19 15:39:13.0

Understanding warpage of package attach locations on PCBs under reflow temperature conditions is critical in surface mount technology. A new industry standard, IPC 9641, addresses this topic directly for the first time as an international standard.This paper begins by summarizing the sections of the IPC 9641 standard, including, measurement equipment selection, test setup and methodology, and accuracy verification. The paper goes further to discuss practical implementation of the IPC 9641 standards. Key advantages and disadvantages between available warpage measurement methods are highlighted. Choosing the correct measurement technique depends on requirements for warpage resolution, data density, measurement volume, and data correlation. From industry experience, best practice recommendations are made on warpage management of PCB land areas, covering how to setup, run, analyze, and report on local area PCB warpage.The release of IPC 9641 shows that flatness over temperature of the package land area on the PCB is critical to the SMT industry. Furthermore, compatibility of shapes between attaching surfaces in SMT, like a package and PCB, will be critical to product yield and quality in years to come.

Akrometrix

BVA: Molded Cu Wire Contact Solution for Very High Density Package-on- Package (PoP) Applications

Technical Library | 2015-01-28 17:39:34.0

Stacking heterogeneous semiconductor die (memory and logic) within the same package outline can be considered for less complex applications but combining the memory and processor functions in a single package has compromised test efficiency and overall package assembly yield. Separation and packaging the semiconductor functions into sections, on the other hand, has proved to be more efficient and, even though two interposers are required, more economical. The separated logic and memory sections are configured with the same uniform outline for vertical stacking (package-on-package). The most common configuration places the logic section as the base with second tier memory section soldered to a mating contact pattern. This paper addresses the primary technological challenges for reducing contact pitch and package-on-package interface technology.

Invensas Corporation

Evaluating the Mechanical Reliability of Ball Grid Array (BGA) Flexible Surface-Mount Electronics Packaging under Isothermal Ageing

Technical Library | 2015-02-12 16:57:56.0

Electronic systems are known to be affected by the environmental and mechanical conditions, such as humidity, temperature, thermal shocks and vibration. These adverse environmental operating conditions, with time, could degrade the mechanical efficiency of the system and might lead to catastrophic failures.The aim of this study is to investigate the mechanical integrity of lead-free ball grid array (BGA) solder joints subjected to isothermal ageing at 150°C for up to 1000 hours. Upon ageing at 150°C the Sn-3.5Ag solder alloy initially age-softened for up to 200 hours. This behaviour was linked to the coarsening of grains. When aged beyond 200 hours the shear strength was found to increase up to 400 hours. This age-hardening was correlated with precipitation of hard Ag3Sn particles in Sn matrix. Further ageing resulted in gradual decrease in shear strength. This can be explained as the combined effect of precipitation coarsening and growth of intermetallic layer. The fractured surfaces of the broken solder balls were also investigated under a Scanning Electron Microscope. The shear failures were generally due to ductile fractures in bulk solders irrespective of the ageing time.

School of Engineering, University of Greenwich

Solder Paste Stencil Design for Optimal QFN Yield and Reliability

Technical Library | 2015-06-11 21:20:29.0

The use of bottom terminated components (BTC) has become widespread, specifically the use of Quad Flat No-lead (QFN) packages. The small outline and low height of this package type, improved electrical and thermal performance relative to older packaging technology, and low cost make the QFN/BTC attractive for many applications.Over the past 15 years, the implementation of the QFN/BTC package has garnered a great amount of attention due to the assembly and inspection process challenges associated with the package. The difference in solder application parameters between the center pad and the perimeter pads complicates stencil design, and must be given special attention to balance the dissimilar requirements

Lockheed Martin Corporation

SMT Troubleshooting Guide

Technical Library | 2018-10-20 13:50:05.0

With this easy-to-use Troubleshooting Guide, you can learn to troubleshoot common SMT issues. After using it a few times, it will become an essential companion for you and anyone in your company responsible for operating an SMT line. This Guide offers troubleshooting advice for common SMT assembly issues by process defect. If your issue is not resolved after following the steps to help identify the possible root cause and solution, please contact your Cookson Electronics representative who will be able to provide you with further assistance.

Cookson Electronics


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