Electronics Forum | Fri Jan 15 09:27:18 EST 1999 | Earl Moon
| I saw the problem of void in solder bump or in lead less component or some BGA. But I didn't have standard specification of that void is accept or reject? Do any body have the better idea or suggestion of the criteria ? | | Thank you, | Wirat
Electronics Forum | Wed Aug 03 21:29:59 EDT 2005 | Ken
Yes, lead can promote fillet lift. In order to understand this defect you must begin looking at your lead frame mateials. some lead frames are more susceptable to this disorder. This is most likely a cte mismatch disorder. Lead contamination in
Electronics Forum | Wed Aug 07 16:33:08 EDT 2013 | rway
I did not see the histogram image (didn't scroll down). My point about the flat metal surfaces is they should have a large white total under top-light with red filter. You should be able to distinguish between the two (fillets and no fillets). I k
Electronics Forum | Tue Jul 02 02:50:55 EDT 2002 | ianchan
Hi mates, was going thru the IPC-A-610C Standards, and noted BGA voids stands somewhere between 10%-25% voids permissible in the solder "ball" bump, after reflow process. Was wondering, hypothetical case study, is there any specification for voids
Electronics Forum | Wed Dec 12 21:43:16 EST 2007 | davef
There is no specification for solder paste height, just as there is no specification for paste volume. Focus on producing a fillet that meets J-STD-001. You make the choices that produce the end result.
Electronics Forum | Wed Aug 07 16:16:49 EDT 2013 | simplycomplex85
The pictures show you what I'm seeing and the settings. There aren't flat metal surfaces. There is a lead and a fillet there. So its shown as black, not white. We are using the red and the histogram.
Electronics Forum | Tue Aug 20 15:36:31 EDT 2013 | sevenzero
http://www.flickr.com/photos/61443293@N03/9555358689 Compiled some screen grabs. The only example I had offline is a top inspection of a TH leg. Same idea. Picture 1: Add Solder Insp. Picture 2: Hist Perams. Adjust bottom slider until what you know
Electronics Forum | Mon Aug 01 06:59:02 EDT 2005 | Joseph
Dear all, We observed visible micro crack at top side of solder fillet during lead free wave solder process. We did not see any visible micro crack at bottom side, and it always located at joints of transformer. Any input be much appreciated. Best
Electronics Forum | Fri Jun 09 07:26:24 EDT 2006 | amol_kane
hi, gald to hear that yr process is working well.....we are in the process of buying a wave with SN100C solder.....any pitfalls/precautions that you took during the transition? did you do any DOE for setting up the profile values?? are you seeing a
Electronics Forum | Wed Aug 23 22:31:17 EDT 2006 | darby
Nope, and, Be careful with the "grid" on your stencil for the big centre pad - I could not find the stencil recommendations. I use a similar part by Cygnal (CP2101). Next time I will reduce the apertures by 50% from their suggested layout. We had fl