Electronics Forum | Mon Sep 17 15:27:51 EDT 2001 | jschake
Challenges: The basic defects that impact assembly yield are bridging, satellite solder balls, and opens (i.e. tombstones / draw bridges). There are many variables with the stencil printing process that can impact these; several of them are listed
Electronics Forum | Fri Apr 30 15:24:12 EDT 1999 | Kevin Hussey
| Ok folk's has anyone used Alpha Metal's UP78 solder paste ? | | Our place is looking to move to that as the way to go, getting rid of the Hereaus 362's and Alpha 737's of the current set up. | | My question's are really : | how is the printabilit
Electronics Forum | Thu Aug 05 11:51:44 EDT 1999 | Wolfgang Busko
| | | | | | | | | | | | Hello, | | | If you are using no-clean and they are entrapped in the flux it is also IPC accepted but i havent found a customer yet who agrees with that. Im sure you have checked your profile. I had the same problem with chi
Electronics Forum | Thu Apr 06 15:47:09 EDT 2006 | jbrower
Last week I had the opportunity to get a sample of AIM SN100C solder paste. The SN100C paste was very nice to work with. My initial observations was that the paste had a very light odor, much less than the Alpha UP78 paste that we are currently
Electronics Forum | Wed Jun 30 13:48:57 EDT 1999 | JohnW
| | | | | | | | | | | | snip | | | | | | | | | | | | | John and Dave, | | | | | | | | | | | | | | Again, I don't work with larger chip devices with this issue. The company I now work with developed a strategy, based on considerable research (as ot
Electronics Forum | Wed Jun 30 15:24:23 EDT 1999 | Earl Moon
| | | | | | | | | | | | | | snip | | | | | | | | | | | | | | | John and Dave, | | | | | | | | | | | | | | | | Again, I don't work with larger chip devices with this issue. The company I now work with developed a strategy, based on considerable res
Electronics Forum | Wed Jun 30 17:52:06 EDT 1999 | JohnW
| | | | | | | | | | | | | | | | snip | | | | | | | | | | | | | | | | | John and Dave, | | | | | | | | | | | | | | | | | | Again, I don't work with larger chip devices with this issue. The company I now work with developed a strategy, based on cons
Electronics Forum | Sat Jan 22 20:59:51 EST 2000 | Jeff Sanchez
Michael, I am not sure if you are trying to lay out a board with vias in the pads or suffer through an assembly you got stuck with? I am building run of boards right now that has vias in most the smt pads. I'm sure the design group thought it was
Electronics Forum | Fri Mar 01 08:35:27 EST 2002 | caldon
I am on board with Dave F.(like I usually am). I can not imagine what IPC specs the auditor is speaking about. The Stencil Design criteria, 610, and 001 do not fit the type of solder deposition you speak of (nor I think they should). The machine para
Electronics Forum | Wed Jun 30 22:00:29 EDT 1999 | Earl Moon
| | | | | | | | | | | | | | | | | | snip | | | | | | | | | | | | | | | | | | | John and Dave, | | | | | | | | | | | | | | | | | | | | Again, I don't work with larger chip devices with this issue. The company I now work with developed a strategy, b
