Electronics Forum: via fill hole short (Page 10 of 13)

Re: double sided boards - process / design issue.

Electronics Forum | Tue Sep 22 13:14:27 EDT 1998 | Chrys

| We are getting into a lot of double sided boards offlate. Our customer is loading a lot of RNETS, Diodes ( MINLS, SOT23s and other 2 leaded diodes ). We are processing it through a traditional glue process and wave soldering the SMT parts along wit

Inspection and splicing

Electronics Forum | Tue Aug 21 08:34:03 EDT 2007 | rgduval

We have the same problems with cut/tape parts. But, we specialize in short-run prototypes, so I don't have much of a choice but to deal with it, and find a way to make it as easy as possible. We just demo'd a splice tool from Sierra Electronics (ww

Re: Help I need DATA on Thermal shock caused by REWORK!

Electronics Forum | Sat Oct 02 03:27:52 EDT 1999 | Brian

| I am currently in the middle of a company wide war and I'm looking for data (AMMO). Here are the problems: | | 1) I am looking for anyone who has done or seen any reports on Thermal Shock to smt parts and/or via holes caused by Soldering Irons at

Re: unsoldered joints

Electronics Forum | Tue Sep 22 12:25:31 EDT 1998 | Chrys

| | Hi Jacqueline! | | Do these joints that you're having problems with happen to be on fine pitch solder joints? Are the fillets staying attached to the foot and separating from the pads cleanly? | | If that is true, are there many vias concen

Gold versus HASL

Electronics Forum | Fri Sep 13 09:16:36 EDT 2002 | bmulcahy

Hi dave, Only back in the forum today to see your query so here goes (1) VIA ,PTH holes -- we found that because the amount of gold being plated is generally less that the amount of HASL that holes can be physically wider. This then (pacticularly o

baking boards, revisited

Electronics Forum | Fri Oct 04 11:34:42 EDT 2002 | Bob Willis

Some additional comments from a paper may be of interest. Baking Printed Circuit Boards - Why and How Baking printed boards prior to conventional and surface mount assembly should not be necessary. Often boards are baked for historical reasons; in

Via holes and Wave Solder

Electronics Forum | Mon Mar 13 14:26:45 EST 2006 | Wave Master Larry

Well, im not sure what plane you guys are on, but I can back up my what im talking about. Ya see I wnet to Soltec traingin back in 1995 for our new wave. I got a diploma proofing that I know what i'm talking about. no one else in my company has on

Re: Thanks.

Electronics Forum | Fri Jun 04 17:26:11 EDT 1999 | C.K.

| | | | Geez, those test guys are always whining about via holes, aren't they? I even had one test guy go over to our finals/add-on department and instruct everone to look for unfilled vias and fill them by hand! Without consulting the area manage

Re: Ionic chromotography test on PCBA

Electronics Forum | Fri Jun 05 10:24:56 EDT 1998 | Earl Moon

| I have just been assigned to look into the ionic chromotograhy test on our PCBA but I have zero knowledge. Could anyone help to explain what is this test about? Is it | a) a destructive test? | b) What is the measurement unit of this test? | c) Wh

Re: DFM / DFT information

Electronics Forum | Thu Jul 13 22:20:38 EDT 2000 | Dave F

=10 mils larger than lead 3 silk screen legend text weight >=10 mils 4 pads >=15 mils larger than finished hole sizes 5 place through hole components on 50 mil grid 6 no silk screen legend text over vias (if vias not solder masked) or holes 7 so


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