ICT and specifying PCBA testing

Agilent TestJet Technology White Paper

In the early 1990s, the testing of digital parts became problematical. Previous in-circuit test techniques sought to ensure a correct, functioning part by applying digital patterns, called vectors, to the inputs of the device, and monitoring the outputs of the device. If the outputs matched the expected patterns, the digital part was deemed to be the correct part, oriented properly, and soldered properly. This technique had two requirements that became difficult to supply by the mid-1990s:

Knowledge of the functioning of the digital part so that an appropriate set of patterns could be generated; and test probe access to every input and output of the device.

The Agilent TestJet technique was patented and introduced by Agilent in 1994 after several after several years of research and refinement. It makes use of a property of most digital ICs in use in the mid-1990s: the lead frame, a metal framework that includes the devices input, output and power pins and their extensions up to the point where the silicon die is attached. The size and shape of the lead frame is fairly stable from device to device and vendor to vendor.

The technique uses an external plate, suspended above the digital part, and separated from the lead frame by the plastic or ceramic material of the device housing. The lead frame and the external plate form a small capacitor that can be measured by stimulation with an ac source. Each pin (inputs, outputs and power) consists of a part of the lead frame, and so each can be detected as a separate capacitance.

The property that makes this technique interesting for in-circuit test shows up when a device pin is not properly soldered to its trace on the board. In this case, there is an additional capacitor in series with the TestJet capacitor. This additional capacitance exists because there is a tiny air gap between pin and trace. This is a very small capacitance, much smaller than the TestJet capacitor. The series combination of the TestJet capacitor and this additional pin capacitor is smaller than either capacitor. So, the TestJet technique seeks to measure the capacitance at each device pin, and identify each pin that is significantly smaller than an expected (computed) value. A threshold value can be set for each pin to discriminate between well- and poorly-soldered connections.

The big advantage of the Agilent TestJet technique is that no knowledge of the core functionality of the device is needed. The technique depends only on physical properties of the packaging. It still requires test probe access to all device pins.

Agilent takes advantage of a particularly stable and low-noise analog measurement system in the Agilent 3070 systems to measure capacitance in the 0-200 femtofarad (1 ff = 10-15 farads) range. There is sufficient repeatability in the measurement to permit excellent discrimination between good and bad solder connections.

reply »

As the article eludes to, you still need probe access to measure the pins with TestJet. One thing I wanted to add was the use of JTAG for use with Boundary Scan. Certain devices have JTAG capability, but not all JTAG devices are Boundary Scan compatible. This is unfortunate, but more and more devices are being supported with Boundary Scan. This allows you to daisy-chain your JTAG ports together and test the I/O properties of the device; thereby, testing for lifted leads as well, if you choose, but complete access is not required. That's the benefit of Boundary Scan, you only need access to the JTAG port. Each I/O pin has a cell that can be tested for proper operation. JTAG then reports where errors occurred in the chain. You could have many devices chained together for testing. This could be supported on your ICT or for use on the bench. Using without probe access however only tests the device, not the bond between pad and lead.

reply »