QFN voiding levels

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We currently have a project requiring us to place multiple Q... - Jun 10, 2010 by muarty

Hi Muarty, We've had a lot of experience with QFN's now. ... - Jun 10, 2010 by Daxman

Thanks Dax, We currently employ a stencil aperture design... - Jun 11, 2010 by muarty

Depending on the how you plug the via, the void level can si... - Jun 15, 2010 by Sean K.

Rather than tent the thermal vias, we use a small annular ri... - Jun 16, 2010 by ScottE

muarty

#62032

QFN voiding levels | 10 June, 2010

We currently have a project requiring us to place multiple QFN devices (of various sizes). The pick an place is not a problem at all, where we are seeing 'problems' is that 3 of the devices are being place on locations where the ground pad have plugged via arrays. Has anyone else had experience with this type of scenario, and if so what sort of results are you experiencing in terms of voiding?

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Daxman

#62035

QFN voiding levels | 10 June, 2010

Hi Muarty,

We've had a lot of experience with QFN's now. Several years ago we started testing various design methods of the via arrays as well as paste apertures to cover the arrays. There has been some time that has passed now since these packages have been used and for the longest time IPC didn't have a spec for the voiding levels. I do believe they are releasing something soon.

Normally, the voiding and solder coverage isn't really a huge problem for components that don't dissipate heat. The vast majority of problems arise from amp circuits that need a solid connection to a ground plane. The via design will vary, depending on the manufacturer of the component, but when you're designing the stencil, try a 30% reduction and try to avoid paste over top of the via's as much as possible. We use a ground aperture design much like BGA apertures, but located where the via's are not. Hope this helps.

-Dax

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muarty

#62041

QFN voiding levels | 11 June, 2010

Thanks Dax,

We currently employ a stencil aperture design pretty much similar to that you describe. And you are correct in what you say about the thermal demands almost dictating the allowable voiding level. We have suggested to our customer that they unplug the vias, as we believe we will see much more consistant results by allowing the volatiles to exit the assembly more easily. As it is a lead free assembly we feel we can control almost exactly where the solder will flow to, our customer has concerns about solder leeching through the vias to the underside of the board.

John

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Sean K.

#62065

QFN voiding levels | 15 June, 2010

Depending on the how you plug the via, the void level can significantly affected. If you have via plugged from the bottom side; i.e. opposite side of the component, you will see alot of void due to entrapped air in the via hole. I found work best when no plugging or tenting on vias. Generally, in this case, you may not have to reduce paste depending on the size of QFN and also proper land pattern and holes evenly distributed since excess solder will flow into the holes but not enough to leach out.

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ScottE

#62067

QFN voiding levels | 16 June, 2010

Rather than tent the thermal vias, we use a small annular ring of soldermask around them and only print paste in the areas between the vias. Any way you go you're going to have voids under QFNs, so we just try to make it repeatable so our designers and thermal modelers know what to plan for.

We're working on one now that really limits our ability to use soldermask rings because of the size and limitations on via location due to RF design. We're going to try it with no soldermask and pull the paste apertures back a few mils from the vias. With SnPb we know we'd lose solder down the vias but we're hoping the lousy spreading of SAC305 will be an advantage in this case.

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