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Probe Mark during ICT

Probe Mark during ICT

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Hello friends , What is the extent of Probe mark allowed... - Jun 01, 2012 by VIKAS

Hello friends , Any leads !! Regards Vikas ... - Jun 04, 2012 by VIKAS

IPC-610 should tell you if the joint is suspect. I would ten... - Jun 04, 2012 by pr

I'm not aware of any such stipulation about witness [probe] ... - Jun 04, 2012 by davef

Actually, if you experience lack of witness marks, you proba... - Jun 04, 2012 by Reese

Dear Dave/pr/Reese, Thank you so much for the information a... - Jun 05, 2012 by VIKAS

How deep is the indent? I would say as long as it is hittin... - Jun 05, 2012 by Reese

VIKAS

#66481

Probe Mark during ICT | 1 June, 2012

Hello friends ,

What is the extent of Probe mark allowed on a assembled board ? Is there any related material on net or standard .Recently we had an issue where the ICT was done and the joints on which the pins were tested had dents on the joints due to probe mark .

Please help to clarify.

Thanks

Vikas

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VIKAS

#66495

Probe Mark during ICT | 4 June, 2012

Hello friends ,

Any leads !!

Regards

Vikas

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#66498

Probe Mark during ICT | 4 June, 2012

IPC-610 should tell you if the joint is suspect. I would tend to think they would not have any negative effect.

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davef

#66500

Probe Mark during ICT | 4 June, 2012

I'm not aware of any such stipulation about witness [probe] marks for assembled boards, per se. Certainly, witness marks should not affect the intended performance of the assembly, you know, like damaging the solder connection or smudging solder material into the vicinity of a trace. So, where assembly requirements are stated to be specific to probing or not, there can be no damage to connections or connectors just like other damage from any other unspecified source.

Certainly, IC fab circles discuss witness marks widely. Board fab circles discuss witness marks much less than IC fab, but do address them in IPC-6012.

IPC-6012B, section 3.5.4.2.2 Round Surface Mount Lads (BGA Pads)"One electrical test probe "witness" mark is allowed within the pristine area for Class 1, 2, and 3."

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Reese

#66508

Probe Mark during ICT | 4 June, 2012

Actually, if you experience lack of witness marks, you probably have a problem. Witness marks are OK and will not affect your assembly. I assume this is an SMT assembly we are talking about, in which case, this is what your test pads are for. You should have enough spring force to penetrate any contaminates left over from the production process such as flux residue (This can be real cumbersome when it comes to ICT). The trick is to find how much spring force is needed for your particular assembly, and this will depend on your process. Too low a force and you will have APC issues, too high, and this could lead to vacuum issues depending on how well your fixture is sealed (gasket fixtures that is). A word of note, a higher spring force will also cause the probes to migrate out of the sockets over time, faster than normal, due to the surface friction when the vacuum is release. I use witness marks as an indication of probe alignment, as well as proof of probe contact. Witness marks are good and are expected.

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VIKAS

#66509

Probe Mark during ICT | 5 June, 2012

Dear Dave/pr/Reese, Thank you so much for the information and this will certainly help me to align on the query .Would like to know further :During Flying probe testing the vias are also observed that they have pin mark on the annular ring due to the testing .Are these also acceptable or any criterias are there .Please advise .

Best regards

Vikas

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Reese

#66517

Probe Mark during ICT | 5 June, 2012

How deep is the indent? I would say as long as it is hitting nothing but net (the solder fill), your fine. Besides, you should notice indents on your solder fillets of components on the top-side as well. This is also expected and acceptable.

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