Pioneer-Dietecs Depaneling Press

My company is considering purchasing a depaneling press from Pioneer-Dietecs. Our initial evaluation has been very positive; however, in a recent meeting a question was raised about the amount of stress induced in the pcb/components during depanel. Pioneer has provided a study done by a previous customer. Does anyone know an allowable/acceptable stress level to compare this to? IPC spec? Our boards are mixed technology with mostly chip components and an SOIC. However, an upcoming project could potentially be used on the same press that would be double sided reflow with multiple SOIC's.

Thanks in advance,

John

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