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Void under QFN TI LMZ20502SILT

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#80717

Void under QFN TI LMZ20502SILT | 20 July, 2018

This question is regarding stencil design: I am having voids under QFN TI P/N LMZ20502SILT. I have attached component pic. Signal pin is 18X16 mils. Center pads are 31 mil sq. Initially I had stencil done with one mil per side reduction on signal pad and ground pad both.(which is 87% solder coverage) We had voids. Second time I kept the same size signal pad but made square rounded edge and reduced ground pad to 51% solder coverage. Results got better but we still have voids. Having a concept of printing, placement and reflow I am still missing something. TI recommends to have 90% solder coverage on the ground pad. Anyone able to help. Greatly appreciate your help in advance.

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#80767

Void under QFN TI LMZ20502SILT | 26 July, 2018

Hi VChauhan,

I'll preface this by saying I am no DaveF.

Voiding can occur when the flux in the paste boils and vapourises, the expanding vapour needing somewhere to go displaces the paste.

So... what we have done in the past: 1) Step the stencil down on this part (less paste, less vapour) 2) Switch to a low voiding paste - we use Koki but I'm sure others do it 3) modily the profile to slow it down the preheat so the flux doesn't explosively degass

Hope that helps,

Rob.

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#80771

Void under QFN TI LMZ20502SILT | 26 July, 2018

Rob, Thank you so much for your suggestions.

Vinod.

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#80784

Void under QFN TI LMZ20502SILT | 27 July, 2018

Adding to Rob's suggestions ...

One of the theories about voiding in thermal / ground pads of BTC is: Solder starts melting at the edge of the pad and moves inward towards the center of the solder mass. This traps flux volatilizes. So, there needs to be little 'roads' for the out-gassing to escape. [not a very elegant description, just my take on it.]

Plus, excess solder paste on thermal / ground pads can lift BTC.

Recommended stencil design [similar to IPC-7093]:

* Solder paste coverage of thermal pads: 50-60%

* Solder paste coverage of I/O pads: 100%

Check the SMTnet Technical Library. Voiding under BTC, LGA etc is a popular topic at technical conferences. So, there might be more there.

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#80785

Void under QFN TI LMZ20502SILT | 27 July, 2018

Dave & Rob,

You guys are great. Appreciate your help.

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#80889

Void under QFN TI LMZ20502SILT | 14 August, 2018

Hello, other colleagues gave you valid ideas. I found it helpful if i reduce the size of the cooling openings. I would suggest making the four big square into very small many diamonds. This would maybe decrease your voiding with 2-4 percent. Btw how much do you have now? Additionally an interesting approach is to try with solder preforms - very small ones on the 4 edges of the thermal pad. This maybe can significantly reduce your voiding. Also expensive way is to get a vacuum oven. I had many issues with voiding and believe me - it is a long battle. I managed to reduce voiding on a thermal pad from 40-50% to 15-25%, which for me was a huge success.

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#80890

Void under QFN TI LMZ20502SILT | 14 August, 2018

Thank you so much.

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#80945

Void under QFN TI LMZ20502SILT | 22 August, 2018

To all good suggestions I will add a few other thoughts:

1. Check PCB design(attached). THis mask clearance there is designed so you have some gas escape plan- verify if your PCB design follows that.

2. You can have a long soak reflow profile to reduce voiding as well as add Nitrogen atmosphere.

3. You could consider to place the part with small offset - this technique will allow gas to escape better.

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Selective Conformal Coating System

Reflow Oven