Printed Circuit Board Assembly & PCB Design SMT Electronics Assembly Manufacturing Forum

Printed Circuit Board Assembly & PCB Design Forum

SMT electronics assembly manufacturing forum.


Via spacing

Views: 488

#83848

Via spacing | 2 December, 2019

What are people using out there for minimum spacing between vias ? We recently came across a PCB manufacturer that wants us to increase our spacing due to their process.

Below is our current spec. that we follow. Spacing between via pad to via pad on External copper layers(min:3 mil, typical: 4 mil, preferable:8 mil)

On same net vias we are using a smaller spacing.

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#83869

Via spacing | 4 December, 2019

You can refer to IPC or other international design standard for distance between Via holes.

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#83877

Via spacing | 4 December, 2019

I looked for some sort of IPC standard regarding this but with no success. I would appreciate if you could share the IPC standard you refer to in your post ?

Thank you.

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#83887

Via spacing | yesterday at 02:15 AM

IPC 2221B mentions a minimum clearance of 0.5 mm between adjacent holes. A drill-to-drill spacing of 20 mils is a standard value in manufacturer design rules.

For small annular rings and pad-to-pad clearance, the minimum via distance is often defined by the drill-to-drill spacing.

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#83889

Via spacing | yesterday at 08:32 AM

Thank you for the quick response. Can you tell me the exact verbage from IPC 2221B regarding via to via spacing ? I have Revision A and couldn't find anything that refers to this ?

Thanks again for your help

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