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CSP and underfill

Mike J

#21304

CSP and underfill | 23 August, 2002

Has anyone done a study or know of one that addresses the flow / no-flow underfill differences for CSP devices. My main interest is in the reliability of the CSP and underfill. Any help would be great. Thanks, Mike

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#21305

CSP and underfill | 23 August, 2002

Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies; John Lau; McGraw-Hill Professional; ISBN: 0071351418; 2000 * Chapter 6. Flip Chip on Board with Conventional Underfills. * Chapter 7. Flip Chip on Board with No-Flow Underfills. * Chapter 8. Flip Chip on Board with Imperfect Underfills.

This is the kind of stuff they yammer-on about endlessly at technical conferences like Semicon, Nepcon, APEX, etc. Have you checked the proceedings of those conferences?

What have you found in the SMTA 'Knowledgebase'? There are definitely papers on underfills there, although I can't say about the specifics.

Have you talked to underfill sales-types? They probably have briefcases full of journal reprints.

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EricD

#21307

CSP and underfill | 23 August, 2002

weve done a few evaluations for the no-flow underfill and for the reliability I think it has already passed MRT L3 @ 220C reflow.

What is it specifically you're interested about the flow u/fill??

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