International Wafer-Level Packaging Conference (IWLPC)




Wed, October 23 - Thu, October 24, 2019


DoubleTree San Jose Airport Hotel, San Jose, California


IWLPC brings together the semiconductor industry’s most respected authorities to address all aspects of wafer-level, 3D device packaging, advanced manufacturing & test technologies.

Addressing wafer-level packaging, 3D, and Advanced Manufacturing & Test technologies, the International Wafer-Level Packaging Conference (IWLPC) has been at the forefront of packaging technology evolution. The conference has a rich history of bringing together attendees from over 16 countries in the heart of Silicon Valley to immerse themselves in the latest technology and business trends. Going into its 14th year, the IWLPC is co-produced by Chip Scale Review, the leading international magazine addressing the semiconductor packaging industry, and SMTA, the distinguished global association representing electronic assembly and manufacturing professionals.

The conference comprises three parallel technical tracks with two full days of presentations on wafer-level packaging, 3D integration, and Advanced Manufacturing & Test. Workshops, keynote speakers, and panel discussions are offered by world-class experts and enable attendees to broaden their technical knowledge. The technical program includes a two-day expo where 60+ exhibitors showcase their latest technologies and products. The conference provides a collective network of over 800 industry professionals, including vendors from leading semiconductor companies, foundries, and OSATs, as well as key technology, equipment, and materials suppliers in the exhibit area. Attendees will be inspired by the quantity and quality of the featured new developments and emerging technologies.


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