High-Speed Digital Design & PCB Layout: Signal Integrity Issues in Today’s Complex Electronic Equipment

The speed of today’s logic devices mandates that the interconnects on PCBs must meet the high switching rise/fall times of these devices. Switching edges are in the 200ps to 300ps range and some devices have edges that have broken the 50ps barrier. This has resulted in high-speed design problems such as:

• A lack of control over impedance and reflections
• Crosstalk and bypassing failures
• Time delays, false triggering and reflections
• Failure to meet EMI and FCC requirements

It is the edge rate, not the frequency, which exacerbates this problem. So, even if your design is for moderate frequency, the edge rates can cause these designs to reflect the high-speed effects.

Most designs today use a microprocessor and today’s micros have clock rates about 400 times higher than the original 8 and 16 bit machines. A key factor is the minimization of the semiconductor device (now at 10 nm) leading to less parasitic L and C and thereby faster switching rates. This phenomenon is also apparent in RAMs, ROMs, ASICs and Gate Arrays. This leads to PCBs requiring terminators, new CAD routing disciplines, and component additions to minimize ground bounce effects. More and more designs are requiring these faster devices to meet more demanding specifications that match or beat the competition.

The course provides you with the knowledge to do it right the first time. The course provides tools for recognizing the problems with any proposed high-speed design. Design rules and design processes are taught that insure the PCB will function properly at the prototype stage. The course emphasizes cost competitive design without sacrificing high-speed integrity.

This course is for anyone who has worked with today’s ICs, high-speed designs and PCB layouts. No advanced math is required though attendees will find it helpful to bring a scientific calculator to the course. The course is not an introductory course. It is presented at a technical level that will provide experienced designers with information to design and layout a high speed PCB.

Who Should Attend: Digital logic engineers, system architects, technicians, PCB layout professionals, IC designers, IC package designers, application engineers, anyone who works with high-speed digital logic, anyone who works with any logic implemented in the submicron processes that are becoming standard in the industry, engineering managers, and project managers.

Instructor:  Robert Hanson, MSEE