SMT Equipment

TestBencher Pro - VHDL, Verilog, and TestBuilder Graphical Test Bench Generation.

TestBencher Pro - VHDL, Verilog, and TestBuilder Graphical Test Bench Generation.

TestBencher Pro - VHDL, Verilog, and TestBuilder Graphical Test Bench Generation.

Name:

TestBencher Pro - VHDL, Verilog, and TestBuilder Graphical Test Bench Generation.

Category:

Software

Offered by:

SynaptiCAD Inc.

Company Information:

SynaptiCAD Inc.

SynaptiCAD aims to help engineers create perfect designs. Since 1992, we have strived to become a company that creates "tools for the thinking mind". This drives all of the interfaces of our tools.

Blacksburg, Virginia, USA

Software Manufacturer

  • Phone 800-804-7073
  • Fax 540-953-3078

SynaptiCAD Inc. website

Company Postings:

(2) products in the catalog

TestBencher Pro - VHDL, Verilog, and TestBuilder Graphical Test Bench Generation. Description:

TestBencher Pro is a graphical test bench generator that dramatically reduces the time required to create and maintain test benches. One of the most time consuming tasks for users of HDL languages is coding test benches to verify the operation of their design. In his book "Writing Testbenches," Janick Bergeron estimates that 70% of design time is spent verifying HDL code models and that the test bench makes up 80% of the total HDL code generated during product development.

TestBencher Pro automates the most tedious aspects of test bench development, allowing you to focus on the design and operation of the test bench. This is accomplished by representing each bus transaction graphically and then automatically generating the code for each transaction. TestBencher makes use of the powerful features of the language that is being generated and the engineer does not have to hand-code each transaction. When hand coding, the designer would have to take the time to deal with the specifics of the design (port information, monitoring system response, etc) as well as common programming errors (race conditions, minor logic errors, and code design problems). This removes a considerable amount of time from the test bench design process because TestBencher manages the low-level details and automatically generates a valid test bench.

TestBencher Pro - VHDL, Verilog, and TestBuilder Graphical Test Bench Generation. was added in Jan 2001

TestBencher Pro - VHDL, Verilog, and TestBuilder Graphical Test Bench Generation. has been viewed 236 times

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