Tessent - Silicon Test and Yield Analysis
Tessent - Silicon Test and Yield Analysis Description:
Tessent combines features of deterministic scan testing, embedded pattern compression, built-in self test, specialized embedded memory test and repair, and boundary scan, as well as board and system-level test technologies.
The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage.
Design Areas: Silicon Test and Yield Analysis
Design Tasks: Logic Test, Memory Test, Mixed-Signal Test, Silicon Learning
The Tessent® Product Suite
Tessent BoundaryScan, Tessent Diagnosis, Tessent FastScan, Tessent LogicBIST, Tessent MemoryBIST, Tessent PLLTest, Tessent SerdesTest, Tessent SiliconInsight, Tessent SoCScan, Tessent TestKompress, Tessent YieldInsight
Tessent - Silicon Test and Yield Analysis was added in Nov 2012
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