JTAGMaster Boundary Scan Tester and Programmer

JTAGMaster Boundary Scan Tester and Programmer Description:

The JTAGMaster Tester and Programmer is a fully integrated solution for the configuration and diagnosis of Programmable Logic Devices (PLDs). This unit includes : * A boundary-scan tester to arbitrarily observe individual pins and therefore determine their functionality. This information can be saved in customisable test procedures which can also include pictures and datasheets. * A programming interface designed to handle industry standard JAM STAPL files (Standard Test And Programming Language) and SVF files (Serial Vector Format) to send programming instructions as well as testing functions to the device. ABI uses the JTAG Standards (Joint Test Action Group, compatible with IEEE1149.1) which ensures compatibility between all compliant ICs.