Cadence Design Systems, Inc.

World's leading EDA company.

Design

Cadence Design Systems is the world's leading EDA company. Cadence customers use our software, hardware, and services to overcome a range of technical and economic hurdles.

Our technologies help customers create mobile devices with longer battery life. Designers of ICs for game consoles and other consumer electronics speed their products to market using our hardware simulators to run software on a ‘virtual’ chip - long before the actual chip exists. We bridge the traditional gap between chip designers and fabrication facilities, so that manufacturing challenges can be addressed early in the design stage. And our custom IC design platform enables designers to harmonize the divergent worlds of analog and digital design to create some of the most advanced mixed-signal system on chip (SoC) designs. These are just a few of the many essential Cadence solutions that drive the success of leading IC and electronic systems companies.

Cadence Design Systems, Inc. Postings

5 technical articles »

Successfully Designing FPGA-Based Systems

Mar 15, 2012 | Nagesh Gupta

Increases in field-programmable gate array (FPGA) capabilities, combined with growing system complexity, have created many FPGA-based system design challenges. One key challenge is choosing the right FPGA for the design needs, and maximizing the use of FP...

Development of a Design & Manufacturing Environment for Reliable and Cost- Effective PCB Embedding Technology

Oct 06, 2011 | M. Brizoux, A. Grivon, W. C. Maia Filho; Thales Corporate Services. J. Stahr, M. Morianz; AT&S. Hemant Shah, Ed Hickey; Cadence Design Systems Inc.

The desire to have more functionality into increasingly smaller size end products has been pushing the PCB and IC Packaging industry towards High Density Interconnect (HDI) and 3D Packaging (stacked dies, embedded packaged components). Many companies in the high-end consumer electronics market place have been embedding passive chip components on inner PCB and IC Packages for a few years now. However, embedding packaged components on inner layers has remained elusive for the broader market due to lack of proper design tools and high cost of embedding components on inner layers (...)

This paper will highlight several key industrialization aspects addressed in the frame of the European funded FP7 HERMES* project to build a manufacturing environment for products with embedded components. The program entered its third year and is now dealing with the manufacturing of functional demonstrators as an introduction to industrialization....

3D ICs With TSVs - Design Challenges And Requirements

Dec 09, 2010 | Cadence

As demands accelerate for increasing density, higher bandwidths, and lower power, many IC design teams are looking up – to 3D ICs with through-silicon vias (TSVs). 3D ICs promise “more than Moore” integration by packing a great deal of functionality int...

Building Differentiated Products Through Shorter, More Predictable Design Cycles.

Feb 25, 2010 | Cadence

This paper will focus on two challenges: building differentiated products, which can enable systems companies to quickly penetrate a market, take a leadership position, and effectively counter or displace any competition; and build them faster. Clear differentiation also allows a superior value proposition, which will enable a stronger position on pricing with less need to circum to eroding ASPs. Differentiation can involve many factors, but this paper will focus on those related to the technology impact/usage that directly enables the design of products with shorter, more predictable design cycles compared to the competition....

Parasitic Extraction for Deep Submicron and Ultra-deep Submicron Designs

Aug 09, 1999 | Cadence Design Systems, Inc.

Shrinking process technologies and increasing design sizes continually challenge design methodologies and EDA tools to develop at an ever-increasing rate. Before the complexities of deep submicron (DSM), gate and transistor delays dominated interconnect delays, and enabled simplified design methodologies that could focus on device analysis. The advent of DSM processes is changing all of this, invalidating assumptions and approximations that existing design methodologies are based upon, and forcing design teams to re-tool. High-capacity parasitic extraction tools are now critical for successful design tape-outs....

1 news release »

Cadence Releases XJTAG DFT Assistant for OrCAD Capture

Nov 15, 2016 | Software interface enables early detection and repair of circuit board errors at the design stage, before hardware is produced.

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