Altera Corporation

Semiconductor Company which design FBGA and its own PCB Board to test our chips.


Programmable Solutions at the Forefront of Innovation

Altera Corporation is at the forefront of technology innovation, providing customers programmable solutions for leading-edge electronic systems that are shaping our modern world.  Headquartered in Silicon Valley, California, Altera has been supplying the industry with access to the latest programmable logic, process technologies, IP cores and development tools for more than 30 years. Altera was founded in 1983 and employs more than 3,000 people in over 20 countries.

Altera’s innovative mindset, combined with technology leadership and operational excellence, enable today’s largest technology and system companies to rapidly and cost effectively innovate, differentiate and win in their markets. The company’s FPGAs, SoCs with embedded processor systems, CPLDs, ASICs, and complementary technologies, such as power solutions, are preferred by more than 12,000 customers worldwide in a variety of end-markets, including communications, networking, cloud computing and storage, industrial, automotive and defense.

Altera Corporation Postings

1 technical article »

Packaging Technology and Design Challenge for Fine Pitch Micro-Bump Cu-Pillar and BOT (Direct Bond on Substrate-Trace) Using TCNCP

Dec 02, 2015 | Myung-June Lee -Altera Corporation, SungSoon Park, DongSu Ryu, MinJae Lee - Amkor Technology, Hank Saiki, Seiji Mori, Makoto Nagai - NTK Technologies.

(Thermal Compression with Non-Conductive Paste Underfill) Method.

The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.

Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).

This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology....

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