DRPIC1655X - Single Cycle High Performance 8-bit RISC Microcontroller, low cost high performance

DRPIC1655X - Single Cycle High Performance 8-bit RISC Microcontroller, low cost high performance Description:

Overview

• 4 times faster compared to original implementation

• the best power use, price and performance combination

• advanced power saving SLEEP mode

The DRPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast, dual ported memory. The core has been designed with a special concern about low power consumption, assuring the best power use, price and performance combination available on the IP cores market.

Our power efficient Core is software-compatible with the industry standard PIC 16XXX Microcontrollers. It implements an enhanced Harvard architecture (separate instruction and data memories), with independent address and data buses. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations, to occur simultaneously. The advantage of this architecture, is that instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data, from the data memory.

The DRPIC1655X architecture is 4 times faster compared to standard architecture. Most instructions are executed within 1 system clock period, except the instructions, which operate directly on PC (GOTO, CALL, RETURN) program counter. This situation requires the pipeline to be cleared and subsequently refilled. This operation takes additional one clock cycle.

Our unique Microcontroller perfectly fits in applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode makes this IP core perfect for applications, where the power consumption aspect is critical.

The DRPIC165X is delivered with fully automated testbench, complete set of tests and DoCD TM on-chip hardware debugger,  allowing easy package validation, at each stage of SoC design flow. Each of the DCD's PIC Core, has built-in support for the DCD Hardware Debug System called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories. More details about DCD on Chip Debugger

Features

■ Software compatible with industry standard PIC16C55X
■ Pipelined Harvard RISC architecture
■ 4 times faster compared to original implementation
■ 35 instructions
■ 14 bit wide instruction word
■ Up to 512 bytes of internal Data Memory
■ Up to 64K bytes of Program Memory
■ Configurable hardware stack
■ Power saving SLEEP mode
■ Fully synthesizable
■ Static synchronous design
■ Positive edge clocking and no internal tri-states
■ Scan test ready
■ Technology independent HDL Source Code
■ 800 MHz virtual clock frequency in a 0.35u technological process

Tech Specs

FPGA - Altera, Xilinx, Lattice

Type - Soft Firm  

Equivalent Part - MICROCHIP PIC16C554 and PIC16C558

Availability - now

TSMC:

Silicon Proven : 180nm (CL018G); 130nm (CL013G)

UMC:

SIlicon Proven : 0.18µm; 130nm

FPGA Technology:

Altera: Stratix II, Stratix GX, Stratix, HardCopy, FLEX 10K, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Spartan-3,
Actel: SX-A, ProASICPLUS, Axcelerator,