DFPAU-DP - Floating Point Arithmetic Coprocessor - Double Precision

DFPAU-DP - Floating Point Arithmetic Coprocessor - Double Precision Description:

Overview

DFPAU-DP is a Floating Point Arithmetic Coprocessor, designed to assist CPU in performing the floating point arithmetic computations. DFPAU-DP directly replaces C software functions, by equivalent, very fast hardware operations, which significantly accelerate system performance. It doesn’t require any programming, so it also doesn’t require any modifications made in the main software. Everything is done automatically during software compilation by the DFPAU-DP C driver.
DFPAU-DP was designed to operate with DCD’s DP8051, but can also operate with any other 8-, 16- and 32-bit processor. Drivers for all popular 8051 C compilers are delivered together with the DFPAU-DP package.
DFPAU-DP uses the specialized algorithms to compute math functions. It supports addition, subtraction, multiplication, division, square root, and comparison. It has built-in conversion instructions from integer type to floating point type and vice versa. The input numbers format is according to IEEE-754 standard. DFPAU-DP supports double and single precision real numbers, 8-bit, 16-bit and 32-bit integers. DFPAU-DP is prepared to use with 8-, 16- and 32-bit processors.
DFPAU-DP is a technology independent design that can be implemented in a variety of process technologies.

Features

■ Direct replacement for C double, float software functions such as: +, -, *, /,==, !=,>=, <=, <, >
■ Configurability of all available functions
■ C interface supplied for all popular compilers: GNU C/C++, 8051 compilers
■ No programming required
■ IEEE-754 Double precision real format support – double type
■ IEEE-754 Single precision real format support – float type
■ 8-bit, 16-bit 32-bit and 52-bit integers format supported – integer types
■ Flexible arguments and result registers location
■ Performs the following functions:
■ FADD, FSUB – addition, subtraction
■ FMUL, FDIV – multiplication, division
■ FSQRT – square root
■ FXAM – examine input data
■ FUCOM – comparison
■ FCLD, FILD – 8-bit, 16-bit integer to dou-ble
■ FLLD, FELD – 32-bit, 52-bit integer to double
■ FCST, FIST – double to 8-bit, 16-bi integer
■ FLST, FEST – double to 32-bit, 52-bit integer
■ FFLD – float to double
■ FFST – double to float
■ Exceptions built-in routines
■  Masks each exception indicator:
■ Precision lack PE
■ Underflow result UE
■ Overflow result OE
■ Invalid operand IE
■ Division by zero ZE
■ Denormal operand DE
■ Fully configurable
■ Fully synthesizable
■ Static synchronous design
■ Positive edge clocking and no internal tri-states
■ Scan test ready

Tech Specs

FPGA - Altera, Xilinx, Lattice

Type - Soft Firm  

Compliant Standard - IEEE-745

Availability - now

FPGA Technology:

Altera: Stratix II, Stratix, Cyclone II, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Virtex-4 SX, Virtex-4 LX, Virtex-4 FX, Spartan-3E, Spartan-3,
Actel: SX-A, ProASICPLUS, Axcelerator,