DF6811 - 8-Bit FAST Microcontroller

DF6811 - 8-Bit FAST Microcontroller Description:

Overview

The DF6811 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. DF6811 soft core is binary-compatible with the industry standard 68HC11 8-bit microcontroller and can achieve a performance 45-100 million instructions per second. There are two available configurations: Harward where data and program buses are separated, and von Neumann with common program and data bus. DF6811 has FAST architecture that is 4.2 times faster compared to original implementation. DF6811 in standard configuration has integrated on chip major peripheral function.
There are two serial interfaces: an asynchro-nous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system has three input capture lines, five output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods.
Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected.
Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the DF6811 IP Core especially attractive for automotive and battery-driven applications.
DF6811 is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

Features

■ FAST architecture, 4.2 times faster than the original implementation
■ Software compatible with industry standard 68HC11
■ 10 times faster multiplication
■ 16 times faster division
■ 256 bytes of remapped System Function Registers space (SFRs)
■ Up to 16M bytes of Data Memory
■ De-multiplexed Address/Data Bus to allow easy memory connection
■ Two power saving modes: STOP, WAI
■ Ready pin alows core operate with slow program and data memories
■ Fully synthesizable
■ Static synchronous design
■ No internal reset generator or gated clock
■ Scan test ready

Deliverables

■ Source code:
■ VHDL Source Code or/and
■ VERILOG Source Code or/and
■ Encrypted, or plain text EDIF netlist
■ VHDL & VERILOG test bench environment
■ Active-HDL automatic simulation macros
■ ModelSim automatic simulation macros
■ Tests with reference responses
■ Technical documentation
■ Installation notes
■ HDL core specification
■ Datasheet
■ Synthesis scripts
■ Example application
■ Technical support
■ IP Core implementation support
■ 3 months maintenance
■ Delivery the IP Core updates, minor and major versions changes
■ Delivery the documentation updates
■ Phone & email support

Tech Specs

Foundry, Node - All technologies

FPGA - Altera, Xilinx, Lattice, ACTEL, others

Type - Soft Firm  

Equivalent Part - Motorola 68HC11

Availability - NOW

FPGA Technology:

Altera: Stratix IV , Stratix III, Stratix II GX, Stratix II, Stratix GX, Stratix, HardCopy Stratix, HardCopy II, HardCopy, Cyclone III, Cyclone II, Cyclone,
Xilinx: Virtex-4, Spartan-6 LX, Spartan-6, Spartan-3E, Spartan-3A, Spartan-3 XA, Spartan-3, Virtex-5, Virtex-6, Virtex-II Pro,
Actel: Axcelerator, IGLOO, Fusion, ProASICPLUS, ProASIC3, RT ProASIC3, RTAX-S/SL/DSP, RTSX-SU, SX-A,