D16950 - Configurable UART with FIFO

D16950 - Configurable UART with FIFO Description:

Overview

The D16950 is a soft core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the OX16C950. The D16950 allows serial transmission in two modes: UART mode and FIFO mode. D16950 is software compatible with 16450, 16550, 16650, 16750 and 16950 standards.

Features

■ Software compatible with 16450, 16550,16650,16750 and 16950 UARTs
■ Configuration capability
■ Separate configurable BAUD clock line
■ Majority Voting Logic
■ Two modes of operation: UART mode and FIFO mode
■ In the FIFO mode transmitter and receiver are each buffered with 128 byte FIFO to reduce the number of interrupts presented to the CPU
■ In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
■ Configurable FIFO size up to 512 levels
■ Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
■ Independently controlled transmit, receive, line status, and data set interrupts
■ False start bit detection
■ 16 bit programmable baud generator
■ Independent receiver clock input
■ MODEM control functions (CTS, RTS, DSR, DTR, RI, DCD)
■ Programmable Hardware Flow Control through RTS and CTS
■ Programmable Flow Control using DTR and DSR
■ Programmable in-band Flow Control using XON/XOFF
■ Programmable special characters detection
■ Trigger levels for TX and RX FIFO
■ Interrupts and automatic in-band and out-off-band flow control
■ Fully programmable serial-interface characteristics:
■ 5-, 6-, 7-, 8- or 9-bit characters
■ Even, odd, or no-parity bit generation and detection
■ 1-, 1½-, or 2-stop bit generation
■ Internal baud generator
■ Detection of bad data in receiver FIFO
■ Clock prescaler from 1 to 31,875
■ Enhanced isochronous clock option
■ 9- bit data mode
■ Software reset
■ Complete status reporting capabilities
■ Line break generation and detection. Internal diagnostic capabilities:
■ Loop-back controls for communications link fault isolation
■ Break, parity, overrun, framing error simula-tion
■ Full prioritized interrupt system controls
■ Fully synthesizable
■ Static synchronous design and no internal tri-states

Deliverables

■ Source code:
■ VHDL Source Code or/and
■ VERILOG Source Code or/and
■ Encrypted, or plain text EDIF netlist
■ VHDL & VERILOG test bench environment
■ Active-HDL automatic simulation macros
■ ModelSim automatic simulation macros
■ Tests with reference responses
■ Technical documentation
■ Installation notes
■ HDL core specification
■ Datasheet
■ Synthesis scripts
■ Example application
■ Technical support
■ IP Core implementation support
■ 3 months maintenance
■ Delivery the IP Core updates, minor and major versions changes
■ Delivery the documentation updates
■ Phone & email support

Tech Specs

Foundry, Node - All

FPGA - All

Type - Soft  

Equivalent Part - OX16C950

Compliant Standard - 16C950

Availability - now

FPGA Technology:

Altera: APEX 20KC, APEX 20KE, Cyclone, Cyclone II, Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III,
Xilinx: Spartan-3, Spartan-3A, Spartan-3E, Virtex-4, Virtex-II Pro,
Actel: Fusion, IGLOO,