SMT Equipment

D16550 - Configurable UART with FIFO

Company Information:

DCD is a leading IP Core provider and SoC design house. The company was founded in 1999 and since the early beginning is considered as an expert in IP Cores architecture improvements.

Bytom, Poland

Consultant / Service Provider

  • Phone +48 32 282 82 66

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(43) products in the catalog



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Digital Core Design


D16550 - Configurable UART with FIFO Description:



The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16550 performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). D16550 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (2^16-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The D16550 has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.
D16550 includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
D16550 is a technology independent design that can be implemented in a variety of process technologies.

The separate BAUD CLK line allow to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency.
The configuration capability allow user to enable or disable during Synthesis process the Modem Control Logic and FIFO's or change the FIFO's size. So in applications with area limitation and where the UART works only in 16450 mode, disabling of Modem Control and FIFO's allow to save about 50% of logic resources.


■ Software compatible with 16450 and 16550 UARTs
■ Two modes of operation: UART mode and FIFO mode
■ Configuration capability
■ Separate configurable BAUD clock line
■ In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU
■ Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
■ In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
■ Independently controlled transmit, receive, line status, and data set interrupts
■ False start bit detection
■ 16 bit programmable baud generator
■ Independent receiver clock input
■ MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
■ Fully programmable serial-interface characteristics:
■ 5-, 6-, 7-, or 8-bit characters
■ Even, odd, or no-parity bit generation and detection
■ 1-, 1½-, or 2-stop bit generation
■ Internal baud generator
■ Complete status reporting capabilities
■ Line break generation and detection. Internal diagnostic capabilities:
■ Loop-back controls for communications link fault isolation
■ Break, parity, overrun, framing error simula-tion
■ Full prioritized interrupt system controls
■ Fully synthesizable
■ Static synchronous design and no internal tri-states


■ Rapid prototyping and time-to-market reduction
■ Design risk elimination
■ Development costs reduction
■ Full customization
■ Global sales network
■ Technology independence
■ Professional service
■ Getting a sillicon proven IP


■ Source code:
■ VHDL Source Code or/and
■ VERILOG Source Code or/and
■ Encrypted, or plain text EDIF netlist
■ VHDL & VERILOG test bench environment
■ Active-HDL automatic simulation macros
■ ModelSim automatic simulation macros
■ Tests with reference responses
■ Technical documentation
■ Installation notes
■ HDL core specification
■ Datasheet
■ Synthesis scripts
■ Example application
■ Technical support
■ IP Core implementation support
■ 3 months maintenance
■ Delivery the IP Core updates, minor and major versions changes
■ Delivery the documentation updates
■ Phone & email support

Tech Specs

FPGA - Altera, Xilinx, Lattice

Type - Soft  

Equivalent Part - PC16550D, TL16C550,

Availability - now

FPGA Technology:

Altera: Stratix II, Stratix GX, Stratix, HardCopy, FLEX 10K, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Spartan-3,

D16550 - Configurable UART with FIFO was added in Apr 2012

D16550 - Configurable UART with FIFO has been viewed 411 times

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