D8259 - Programmable Interrupt Controller

D8259 - Programmable Interrupt Controller Description:

Overview

The D8259 is a soft Core of Programmable Interrupt Controller. It is fully compatible with the 82C59A device. The D8259 Core manages up to 8-vectored priority interrupts for processor. Programming it to cascade allows for up to 64 vectored interrupts. More than 64 vectored interrupts can be accom-plished by programming to Poll Command Mode. D8259 can operate in all 82C59A modes, and supports all 82C59A features: The D8259 can operate in all 82C59A modes, and supports all 82C59A features:

* MCS-80/85 and 8088/8086 processor modes
* Fully nested mode and special fully nested mode
* Special mask mode
* Buffered mode
* Pool command mode
* Cascade mode with master or slave se-lection
* Automatic end-of-interrupt mode
* Specific and non-specific end-of-interrupt commands
* Automatic and Specific Rotation
* Edge and level triggered interrupt input modes
* Reading of interrupt request register (IIR) and in-service register (ISR) through data bus
* Writing and reading of interrupt mask register (IMR) through data bus

D8259 Package includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

D8259 Core is a technology independent design that can be implemented in a variety of process technologies.

Features

■ 8 vectored priority interrupts
■ Up to sixty-four vectored priority interrupts with cascading
■ Support for all 82C59A modes features
■ MCS-80/85 and 8088/8086 processor modes
■ Fully nested mode and special fully nested mode
■ Special mask mode
■ Buffered mode
■ Pool command mode
■ Cascade mode with master or slave selec-tion
■ Automatic end-of-interrupt mode
■ Specific and non-specific end-of-interrupt commands
■ Automatic and Specific Rotation
■ Edge and level triggered interrupt input modes
■ Reading of interrupt request register (IIR) and in-service register (ISR) through data bus
■ Fully synthesizable HDL Source Code
■ Static design and no internal tri-states

Benefits
 

■ Getting a silicon proven and technologically independent IP (VHDL and Verilog)
■ Rapid prototyping and time-to-market reduction
■ Design risk elimination
■ Development costs reduction
■ Full customization
■ Global sales network
■ Professional service
■ Fast responsive support

Deliverables
 

■ Source code:
■ VHDL Source Code or/and
■ VERILOG Source Code or/and
■ Encrypted, or plain text EDIF netlist
■ VHDL & VERILOG test bench environment
■ Active-HDL automatic simulation macros
■ ModelSim automatic simulation macros
■ Tests with reference responses
■ Technical documentation
■ Installation notes
■ HDL core specification
■ Datasheet
■ Synthesis scripts
■ Example application
■ Technical support

Tech Specs

Type - Soft Firm  

Equivalent Part - Intel 82C59A

Availability - NOW

FPGA Technology:

Altera: Stratix II, Stratix GX, Stratix, HardCopy, FLEX 10K, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Spartan-3,
Actel: SX-A, ProASICPLUS, Axcelerator,