Nepes offers flip chip package technology with service offerings, incluing bumping and packaging for flat panel display, solder bumping, wafer level packaging, and high-end fan-out packaging.
As a total solution provider for the back-end processing of FPD driver IC NEPES provides a proven gold bumping technology for LCD, PDP and OLED applications, where higher performance, high density and aggressive form factor are critical. NEPES can provide various turn-key solutions, ranging from bumping, probe test to final packaging of TCP & COF.
Recently, a state of the art gold bumping technology was successfully applied to image sensor devices for mobile camera-phone applications. NEPES is also a technology leader in solder and copper wafer bumping as well as pad redistribution using our propriety bumping technology. Our SMT compatible bumping offers a fine pitch of 50um as well as lead-free & flux-less soldering processes which is very environmentally friendly.
Redistribution process lets I/O bond pads relocate from the perimeter footprint to as area array so that you can transition a wire-bond design to a flip-chip design without having to redesign the die.
This technology leads to true chip size packaging solution called wafer level chip size package(WLCSP)
Nepes is committed to providing worldwide customers with comprehensive test solutions for display driver IC(LCD, Organic EL, PDP) from wafer test to final package test.
Our strength results from in-house test program development by experienced human resource and stable handling/probing system providing high testing yield and services with quick turnaround times. We have experiences to develop the test program with many fabless and IC manufacturing company from the early stage of device development to mass production.
Nepes Corporation Postings
Jul 02, 2014 | Jong-Myeong Park, Seung-Hyun Kim, Young-Bae Park - Andong National University, Myeong-Hyeok Jeong - NEPES Corporation.
Growth behaviors of intermetallic compounds (IMCs) and Kirkendall voids in Cu/Sn/Cu microbump were systematically investigated by an in-situ scanning electron microscope observation. Cu–Sn IMC total thickness increased linearly with the square root of the annealing time for 600 h at 150°C, which could be separated as first and second IMC growth steps. Our results showed that the growth behavior of the first void matched the growth behavior of second Cu6Sn5, and that the growth behavior of the second void matched that of the second Cu3Sn. It could be confirmed that double-layer Kirkendall voids growth kinetics were closely related to the Cu–Sn IMC growth mechanism in the Cu/Sn/Cu microbump, which could seriously deteriorate the mechanical and electrical reliabilities of the fine-pitch microbump systems...