Technical Library | 2023-01-17 17:58:36.0
Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. In emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It's crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.
Technical Library | 2017-06-29 15:41:36.0
What's the most cost-effective method for testing prototype PCBs? Should the assembler do it, or the client's in-house engineers? This article explains all.
Technical Library | 2024-06-19 14:23:36.0
These guidelines on long-term storage are intended to help develop a supply strategy for components which need to be warehoused, processed and used beyond ...
Technical Library | 2024-11-06 16:37:36.0
The difference between the two manufacturing methods with pros and cons to using each.
Technical Library | 2007-01-31 12:08:36.0
Air-powered dispensing systems use controlled pulses of air pressure to dispense solder paste from syringe reservoirs in uniform amounts. In this paper, EFD explains the most critical variables affecting air-powered dispensing of solder pastes and shows how to manage those variables to your advantage.
Technical Library | 2008-10-09 00:06:36.0
This article examines stamp soldering, a solution that provides consistent high quality by repeatedly applying accurate amounts of molten solder onto a printed circuit board using static volumetric solder stamps guaranteeing total flatness during the through-hole soldering process.
Technical Library | 2013-10-21 08:53:36.0
Having been in the wire processing business for 30 years, I have seen a lot of changes and improvements made possible, primarily by advances in electronics and software. Looking ahead, I see continued improvements in efficiency through networking technology.
Technical Library | 2016-09-19 20:26:36.0
This white paper seeks to set out the value of a ‘smarter’ approach to the reflow process and how a more intelligent oven can offer real added value and performance to the entire line. It also lays out some of the criteria that is important when selecting smart equipment for a smart process, that conforms to, and is ready for, IoM or Industry 4.0
Technical Library | 2019-08-09 00:06:36.0
Working with SCADA systems when not properly trained and qualified can be almost as dangerous as working with PLCs without proper PLC training. Some times it can be even more costly to a company. This article explains the best way to learn SCADA systems, also the most cost-effective way! Read to learn how to select the best, what to look for in a SCADA course.
Technical Library | 1999-08-05 10:45:36.0
In 1998, the International 300 mm Initiative (I300I) demonstration and characterization programs will focus on 180 nm technology capability. To support these activities, I300I and equipment supplier demonstration partners must use starting silicon wafers with key parameters specified at a level appropriate level for 180 nm processing, including contamination and lithographic patterning. This document describes I300I's silicon wafer specifications, as developed with the I300I Silicon Working Group (member company technical advisors) and SEMI Standards.
