Technical Library | 2022-06-20 21:01:37.0
We've been doing a lot of print testing in our lab. In our first set of published results, "The Impact of Reduced Solder Alloy Powder Size on Solder Paste Print Performance1" from IPC/APEX 2016, we revealed a hierarchy of input variables to maximize solder paste transfer efficiency and minimize variation. In that study, we used a fully-optioned stencil as part of the equipment set. In order to tease out the data we were looking for, we could not lose critical information to the noise of stencil-induced variations.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
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