Technical Library | 2023-01-17 17:22:28.0
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products. This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC- 9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Technical Library | 1999-05-06 13:44:43.0
This paper explores the direction in which IC technology is headed, highlights potential roadblocks and possible solutions, and discusses some of the physical considerations that could determine the ultimate limits of integration.
Technical Library | 2011-08-04 19:29:53.0
This work covers two major projects aimed at increasing quality and efficiency on a high mix, low volume surface mount electronics production line. Specifically the installation of a ten zone reflow oven and an enhanced changeover method for SMT pick and
Technical Library | 2013-01-11 16:51:33.0
There have been claims in the industry that laser-cut electroformed nickel foil blanks provide stencil print performance comparable to electroformed stencils. A study was established to measure the quantitative differences in performance between the two during an independent lab study.
Technical Library | 2015-10-22 17:37:28.0
The objective of this study is to evaluate conformal coatings for mitigation of tin whisker growth. The conformal coatings chosen for the experiment are acrylic, polyurethane and parylene. Also included in this paper are tin whisker inspection results of tin-plated braiding and wire that was exposed to an environment of 50°C with 50% relative humidity for over five years.
Technical Library | 2021-01-06 20:28:58.0
Cavity technology in a Printed Circuit Board (PCB) has existed for many years. The methodology to create the cavity in the PCB has evolved over time as technologies have advanced and the manufacturing process varies by the individual PCB
Technical Library | 1999-05-06 13:38:45.0
This paper traces the key steps that led to the invention of the integrated circuit (IC). The first part of this paper reviews the steady improvements in the performance and fabrication of single transistors in the decade after the Bell Labs breakthrough work in 1947. It sketches the various developments needed to produce a practical IC. In addition, the more advanced processes such as diffusion, oxide masking, photolithography, and epitaxy, which culminated in the planar process, are summarized.
Technical Library | 1999-05-09 12:36:40.0
The production of electronics began with hand soldering, followed by manual cleaning, which reached its peak during the NASA program. Each step in the process tended to be considered on a stand alone basis, without thought being given to the preceding and following steps. Since each step had its own set of specifications, this led to a "patchwork" approach to overall quality.
Technical Library | 2000-06-21 17:55:59.0
There was once a time when precision cleaning required minimal thought. Just about anything that was dirty could be placed inside a vapor degreaser and emerge clean and dry in a matter of minutes. Today, precision cleaning decisions are seemingly endless with ever-changing environmental regulations, user safety issues and product compatibility concerns. Technologies range from spray-in-atmosphere to ultrasonics to spray under immersion using aqueous, solvent or semiaqueous chemistries. Which method works and with what chemistry? Will the process be safe or even allowed by the regulating agencies?
Technical Library | 2012-10-25 16:34:02.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper will examine stencil technologies (including Laser and Electroform), Aperture Wall coatings (including Nickel-Teflon coatings and Nano-coatings), and how these parameters influence paste transfer for miniature devices with Area Ratios less than the standard recommended lower limit of .5. A matrix of print tests will be utilized to compare paste transfer and measure the effectiveness of the different stencil configurations. Area Ratios ranging from .32 to .68 will be investigated.
