Electronics Forum: 003 (Page 1 of 13)


Electronics Forum | Tue Sep 24 13:03:51 EDT 2019 | davef

IPC-J-STD-003C: Solderability Tests for Printed Boards [ https://shop.ipc.org/IPC-J-STD-003C-WAM1-2-English-D ]

BGA Straight crack

Electronics Forum | Tue Feb 26 07:54:27 EST 2002 | vincent_f

3um 0.03um


Electronics Forum | Fri Feb 15 18:51:13 EST 2013 | hegemon

My hat in the ring too, but with ALL pads showing 95% coverage or better. Slightly different interpretation! 'hege

Solderability problems with gold plated PCB's

Electronics Forum | Thu Nov 12 11:21:42 EST 2015 | davef

IPC J-STD-003. Solderability Tests for Printed Boards

Solderability test - OSP

Electronics Forum | Thu Feb 11 20:38:47 EST 2016 | davef

Try: * J-STD-003 “Solderability Tests for Printed Boards” * IPC-4555 OSP Finish Specification

0.003 track PCB's

Electronics Forum | Fri Oct 15 03:54:38 EDT 1999 | Gregor McInnes

Does anybody Know of a U.K. vendor who can supply Multilayer boards of up to 14+ layers at track and gap sizes of 0.003"? Even European vendors would be good. Curently we have to go to the states for this level of board and it is throwing our commit


Electronics Forum | Wed Oct 17 12:26:42 EDT 2007 | jmelson

.030 Inch? Are you sure? I seriously doubt .030" stainless foil can be etched with any usable result. Do you mean .003" or .030 mm (pretty thin). I've been using .005" brass shim stock, but I am going to .003" now, but I know there are companies

removing solder from a 0.015" hole

Electronics Forum | Wed Feb 26 18:48:01 EST 2003 | kennyg

I'm trying to solder a 0.011" lead into a 0.015" +/-0.003" hole. Stop laughing please. This is normally possible with difficulty, except if the lead is removed and the attempt is made to re-install a lead. Anyone have thoughts on how to remove nea

Clearence of solder resist from QFP Leads

Electronics Forum | Fri Jan 09 09:43:48 EST 2009 | boardhouse

Hi Simon, The main reason that it would probably be removed would be do to lack of clearance for a soldermask dam from pad to pad. typically if the clearance from pad to pad is under .008 the solder mask dam would be removed. Min recomended dam siz


Electronics Forum | Fri Feb 15 14:38:59 EST 2013 | bmario

Hi, We are having a problem with the interpretation of the surface evaluation criteria of J-STD-003 section "A minimum of 95% of each of the surfaces (i.e. each pad) being tested shall exhibit good wetting. The balance of the surface may

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