Electronics Forum | Fri Dec 03 04:20:18 EST 2010 | grahamcooper22
Hi In Dec 2008 the IPC J STD 004 was updated to 004B, and I am wondering what the new test conditions are for testing flux Surface Insulation Resistance and Electro Migration Potential within the new spec. I am looking for the recommended test temp
Electronics Forum | Tue Jul 09 06:11:15 EDT 2019 | alpha1
I would check the clearance between the bottom guide and the carrier clip. Usually I set it .004 below the clop then set the head height .004 above the guide. It's a little tighter than UIC specs but it'll prevent the lead better.
Electronics Forum | Mon Apr 09 14:53:19 EDT 2007 | flipit
Hi, We were running with few defects with lead solder paste. The lead solder paste with stencil 0.010" X 0.020" and 0.004" thick stencil produced near defect free PCB assys. 0.010" X 0.020" (0.004" thick) lead = defect free 0.010" X 0.020" (0.005"
Electronics Forum | Thu Dec 24 13:29:19 EST 1998 | Chris Grendler
| | Anyone ever attach gold bump flip chip to FR4 or Alumina substrates. Am trying to find a solder which is acceptable for use on gold. Am worried about gold imbrittlement since the gold bumps on the flip chip are .004"x.004"x.001" solid gold. The
Electronics Forum | Fri Apr 06 10:43:57 EDT 2007 | flipit
Hi, Anyone seeing difficulty is soldering MLFs or QFN with lead free solder? I have an MLF with 3 rows of pads on each of the 4 sides of the part and then the large center ground plane in the middle. The part is 20 mil pitch. Had good luck with l
Electronics Forum | Sun Jul 05 12:32:43 EDT 2009 | emanuel
While moving to a new location we had to remove the tables from a Philips Comet in order to be able to pass a narrow door. While attempting to calibrate the machine, during Warm-Up a strange error appears, sometimes almost immediately and sometimes a